CY7C1012AV33

512 K × 24 Static RAM

Cypress Semiconductor Corporation

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198 Champion Court

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San Jose

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408-943-2600

Document Number: 38-05254 Rev. *H

Revised June 7, 2011

512 K × 24 Static RAM

Features

Functional Description

The CY7C1012AV33 is a high-performance CMOS static RAM

organized as 512 K words by 24 bits. Each data byte is

feature that significantly reduces power consumption when

deselected.

Writing the data bytes into the SRAM is accomplished when the

chip select controlling that byte is LOW and the write enable input

(WE) input is LOW. Data on the respective input/output (I/O) pins

is then written into the location specified on the address pins

LOW will write all 24 bits of data into the SRAM. Output enable

(OE) is ignored while in WRITE mode.

Data bytes can also be individually read from the device.

Reading a byte is accomplished when the chip select controlling

that byte is LOW and write enable (WE) HIGH while output

enable (OE) remains LOW. Under these conditions, the contents

of the memory location specified on the address pins will appear

on the specified data input/output (I/O) pins. Asserting all the chip

selects LOW will read all 24 bits of data from the SRAM.

state when all the chip selects are HIGH or when the output

enable (OE) is HIGH during a READ mode. For further details,

refer to the truth table of this data sheet.

The CY7C1012AV33 is available in a standard 119-ball PBGA.

COLUMN

DECODER

INPUT BUFFER

512K x 24

ARRAY

OE

WE

CONTROL LOGIC

Functional Block Diagram

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