CY7C1325G

Document Number: 38-05518 Rev. *H

Page 11 of 21

Automatic CE

power-down

current—TTL inputs

inputs switching

7.5 ns cycle, 133 MHz

–

90

mA

10 ns cycle, 100 MHz

–

80

mA

Automatic CE

power-down

current—CMOS inputs

f = 0, inputs static

All speeds

–

40

mA

Automatic CE

power-down

current—CMOS inputs

7.5 ns cycle, 133 MHz

–

75

mA

10 ns cycle, 100 MHz

–

65

mA

Automatic CE

power-down

current—TTL inputs

f = 0, inputs static

All speeds

–

45

mA

Capacitance[10]

Parameter

Description

Test Conditions

100-pin TQFP

Max

119-ball BGA

Max

Unit

Input capacitance

55

pF

Clock input capacitance

5

5

pF

Input/output capacitance

5

7

pF

Thermal Resistance[10]

Parameter

Description

Test Conditions

100 TQFP

Package

119 BGA

Package

Unit

Thermal resistance

(junction to ambient)

Test conditions follow standard test

methods and procedures for

measuring thermal impedance, per

EIA/JESD51.

30.32

34.1

°C/W

Thermal resistance

(junction to case)

6.85

14.0

°C/W

Parameter

Description

Test Conditions

Min

Max

Unit

Figure 3. AC Test Loads and Waveforms

Note

10. Tested initially and after any design or process change that may affect these parameters.

OUTPUT

R = 317



R = 351



5pF

INCLUDING

JIG AND

SCOPE

(a)

(b)

OUTPUT

3.3 V

ALL INPUT PULSES

GND

90%

10%

90%

10%

 1 ns

 1 ns

(c)

OUTPUT

R = 1667



R = 1538



5pF

INCLUDING

JIG AND

SCOPE

(a)

(b)

OUTPUT

2.5 V

ALL INPUT PULSES

GND

90%

10%

90%

10%

 1 ns

 1 ns

(c)

3.3 V I/O Test Load

2.5 V I/O Test Load

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