CY7C1460AV33

CY7C1462AV33

Document Number: 38-05353 Rev. *I

Page 6 of 28

Pin Definitions

Pin Name

I/O Type

Pin Description

A0

A1

A

Input-

synchronous

Address inputs used to select one of the address locations. Sampled at the rising

edge of the CLK.

Input-

synchronous

Byte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM.

WE

Input-

synchronous

Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.

This signal must be asserted LOW to initiate a write sequence.

ADV/LD

Input-

synchronous

Advance/load input used to advance the on-chip address counter or load a new

address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced.

When LOW, a new address can be loaded into the device for an access. After being

deselected, ADV/LD should be driven LOW to load a new address.

CLK

Input-

clock

Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with

CEN. CLK is only recognized if CEN is active LOW.

Input-

synchronous

Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

Input-

synchronous

Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in

Input-

synchronous

Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

OE

Input-

asynchronous

Output enable, active LOW. Combined with the synchronous logic block inside the device

to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as

outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is

masked during the data portion of a write sequence, during the first clock when emerging

from a deselected state and when the device has been deselected.

CEN

Input-

synchronous

Clock enable input, active LOW. When asserted LOW the clock signal is recognized by

the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN

does not deselect the device, CEN can be used to extend the previous cycle when required.

I/O-

synchronous

Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is

triggered by the rising edge of CLK. As outputs, they deliver the data contained in the

direction of the pins is controlled by OE and the internal control logic. When OE is asserted

condition. The outputs are automatically tristated during the data portion of a write

sequence, during the first clock when emerging from a deselected state, and when the

device is deselected, regardless of the state of OE.

I/O-

synchronous

MODE

Input strap pin

Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst

order. Pulled LOW selects the linear burst order. MODE should not change states during

operation. When left floating MODE defaults HIGH, to an interleaved burst order.

TDO

JTAG serial output

synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

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