CY7C1461AV33

CY7C1463AV33, CY7C1465AV33

Document #: 38-05356 Rev. *I

Page 9 of 34

Pin Definitions

Pin Name

IO

Description

Input-

Synchronous

Address Inputs. Used to select one of the address locations. Sampled at the rising edge of the

Input-

Synchronous

Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on

the rising edge of CLK.

WE

Input-

Synchronous

Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This

signal must be asserted LOW to initiate a write sequence.

ADV/LD

Input-

Synchronous

Advance or Load Input. Used to advance the on-chip address counter or load a new address.

When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a

new address can be loaded into the device for an access. After deselecting, drive ADV/LD LOW

to load a new address.

CLK

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK

is only recognized if CEN is active LOW.

CE1

Input-

Synchronous

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with

Input-

Synchronous

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

Input-

Synchronous

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with

OE

Input-

Asynchronous

Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic block

inside the device to control the direction of the IO pins. When LOW, the IO pins are allowed to

behave as outputs. When deasserted HIGH, IO pins are tri-stated and act as input data pins. OE

is masked during the data portion of a write sequence, during the first clock when emerging from

a deselected state, and when the device is deselected.

CEN

Input-

Synchronous

Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the

SRAM. When deasserted HIGH the clock signal is masked. Because deasserting CEN does not

deselect the device, use CEN to extend the previous cycle when required.

ZZ

Input-

Asynchronous

ZZ “Sleep” Input. This active HIGH input places the device in a non time critical sleep condition

with data integrity preserved. During normal operation, this pin has to be LOW or left floating. ZZ

pin has an internal pull down.

IO-

Synchronous

Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by

the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified

by the addresses presented during the previous clock rise of the read cycle. The direction of the

pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH,

the data portion of a write sequence, during the first clock when emerging from a deselected state,

and when the device is deselected, regardless of the state of OE.

IO-

Synchronous

MODE

Input Strap Pin Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence.

Power Supply Power Supply Inputs to the Core of the Device.

IO Power

Supply

Power Supply for IO Circuitry.

Ground

Ground for the Device.

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