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CY7C1472BV33 Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY7C1472BV33 Datasheet(HTML) 9 Page - Cypress Semiconductor |
9 / 33 page CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev. *H Page 9 of 33 TDI JTAG Serial Input Synchronous Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. TMS Test Mode Select Synchronous This pin Controls the Test Access Port State Machine. Sampled on the rising edge of TCK. TCK JTAG Clock Clock Input to the JTAG Circuitry. VDD Power Supply Power Supply Inputs to the Core of the Device. VDDQ IO Power Supply Power Supply for the IO Circuitry. VSS Ground Ground for the Device. Should be connected to ground of the system. NC – No Connects. This pin is not connected to the die. NC(144M, 288M, 576M, 1G) – These Pins are Not Connected. They are used for expansion to the 144M, 288M, 576M, and 1G densities. ZZ Input- Asynchronous ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull-down. Pin Definitions (continued) Pin Name IO Type Pin Description [+] Feedback |
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Similar Description - CY7C1472BV33 |
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