CY7C1472BV33 datasheet(9/33 Pages) CYPRESS

Part #	CY7C1472BV33

Description	72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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9 / 33 page

CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Document #: 001-15031 Rev. *H

Page 9 of 33

TDI

JTAG Serial Input

Synchronous

Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK.

TMS

Test Mode Select

Synchronous

This pin Controls the Test Access Port State Machine. Sampled on the rising edge of TCK.

TCK

JTAG Clock

Clock Input to the JTAG Circuitry.

VDD

Power Supply

Power Supply Inputs to the Core of the Device.

VDDQ

IO Power Supply Power Supply for the IO Circuitry.

VSS

Ground

Ground for the Device. Should be connected to ground of the system.

NC

–

No Connects. This pin is not connected to the die.

NC(144M,

288M,

576M, 1G)

–

These Pins are Not Connected. They are used for expansion to the 144M, 288M, 576M, and

1G densities.

ZZ

Input-

Asynchronous

ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition

with data integrity preserved. During normal operation, this pin must be LOW or left floating.

ZZ pin has an internal pull-down.

Pin Definitions (continued)

Pin Name

IO Type

Pin Description

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Cypress Semiconductor	CY7C1472BV33	902Kb / 30P	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
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CY7C1472BV33 Datasheet(PDF) 9 Page - Cypress Semiconductor

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