CY7C1474BV33-200BGXC datasheet(11/33 Pages) CYPRESS

Part #	CY7C1474BV33-200BGXC

Description	72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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11 / 33 page

CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Document #: 001-15031 Rev. *H

Page 11 of 33

load the initial address, as described in Single Write Accesses

on page 10. When ADV/LD is driven HIGH on the subsequent

clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs

are ignored and the burst counter is incremented. The correct

BW (BWa,b,c,d for CY7C1470BV33, BWa,b for CY7C1472BV33,

and BWa,b,c,d,e,f,g,h for CY7C1474BV33) inputs must be driven

in each cycle of the burst write to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places

the SRAM in a power conservation “sleep” mode. Two clock

cycles are required to enter into or exit from this “sleep” mode.

While in this mode, data integrity is guaranteed. Accesses

pending when entering the “sleep” mode are not considered valid

nor is the completion of the operation guaranteed. The device

must be deselected before entering the “sleep” mode. CE1, CE2,

and CE3, must remain inactive for the duration of tZZREC after the

ZZ input returns LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

Second

Address

Third

Address

Fourth

Address

A1, A0

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

Linear Burst Address Table (MODE = GND)

First

Address

Second

Address

Third

Address

Fourth

Address

A1, A0

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min

Max

Unit

IDDZZ

Sleep mode standby current

ZZ

 VDD 0.2 V

–

120

mA

tZZS

Device operation to ZZ

ZZ

VDD  0.2 V

–

2tCYC

ns

tZZREC

ZZ recovery time

ZZ

 0.2 V

2tCYC

–ns

tZZI

ZZ active to sleep current

This parameter is sampled

–

2tCYC

ns

tRZZI

ZZ Inactive to exit sleep current

This parameter is sampled

0

–

ns

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Cypress Semiconductor	CY7C1474BV33-200BGXC	902Kb / 30P	72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
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CY7C1474BV33-200BGXC Datasheet(PDF) 11 Page - Cypress Semiconductor

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