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CY7C4261V Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CY7C4261V Datasheet(HTML) 10 Page - Cypress Semiconductor |
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10 / 22 page  CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Document #: 38-06013 Rev. *F Page 10 of 22 Switching Characteristics Over the Operating Range Parameter Description 7C4261/71/81/91V- 10 7C4261/71/81/91V- 15 7C4261/71/81/91V- 25 Unit Min Max Min Max Min Max tS Clock cycle frequency – 100 – 66.7 – 40 MHz tA Data access time 2 8 2 10 2 15 ns tCLK Clock cycle time 10 – 15 – 25 – ns tCLKH Clock HIGH time 4.5 – 6 – 10 – ns tCLKL Clock LOW time 4.5 – 6 – 10 – ns tDS Data set-up time 3.5 – 4 – 6 – ns tDH Data hold time 0 – 0 – 1 – ns tENS Enable set-up time 3.5 – 4 – 6 – ns tENH Enable hold time 0 – 0 – 1 – ns tRS Reset pulse width[10] 10 – 15 – 25 – ns tRSS Reset set-up time 8 – 10 – 15 – ns tRSR Reset recovery time 8 – 10 – 15 – ns tRSF Reset to flag and output time – 10 – 15 – 25 ns tOLZ Output enable to output in Low Z[10] 0 – 0 – 0 – ns tOE Output enable to output valid 3 7 3 10 3 12 ns tOHZ Output enable to output in High Z[11] 3 7 3 8 3 12 ns tWFF Write clock to Full flag – 8 – 10 – 15 ns tREF Read clock to Empty flag – 8 – 10 – 15 ns tPAF Clock to programmable Almost-Full flag – 8 – 10 – 15 ns tPAE Clock to programmable Almost-Full flag – 8 – 10 – 15 ns tSKEW1 Skew time between read clock and write clock for Empty flag and Full flag 5 – 6 – 10 – ns tSKEW2 Skew time between read clock and write clock for Almost-Empty flag and Almost-Full flag 10 – 15 – 18 – ns Notes 10. Pulse widths less than minimum values are not allowed. 11. Values guaranteed by design, not currently tested. [+] Feedback |
Similar Part No. - CY7C4261V_11 |
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