CY7C1474V25-200BGXI datasheet(6/31 Pages) CYPRESS

Part #	CY7C1474V25-200BGXI

Description	72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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6 / 31 page

CY7C1470V25

CY7C1472V25

CY7C1474V25

Document Number: 38-05290 Rev. *L

Page 6 of 31

Pin Configurations (continued)

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

12

3

4

5

6

7

8

9

11

10

DQg

DQc

NC

DQPg

DQh

DQd

DQPd

DQPc

DQc

NC

DQh

DQPh

DQd

DQb

DQf

NC

DQPf

DQa

DQe

DQPa

DQPb

DQf

NC

DQa

DQPe

DQe

AA

A

NC

NC/144M

A

NC/288M

A

AA

A

A1

A0

A

AA

A

NC/576M

NC

BWSb

BWSf

BWSe

BWSa

BWSc

BWSg

BWSd

BWSh

TMS

TDI

TDO

TCK

NC

MODE

NC

CEN

VSS

NC

CLK

NC

VSS

VDD

VSS

NC/1G

VDD

NC

OE

CE3

CE1

CE2

ADV/LD

WE

VSS

ZZ

VSS

NC

VDDQ

VSS

NC

VSS

NC

VSS

VDDQ

NC

VDDQ

NC

VDDQ

NC

VDDQ

209-ball FBGA (14 × 22 × 1.76 mm) Pinout

CY7C1474V25 (1 M × 72)

Pin Definitions

Pin Name

I/O Type

Pin Description

A0

A1

A

Input-

synchronous

Address inputs used to select one of the address locations. Sampled at the rising edge of

the CLK.

BWa

BWb

BWc

BWd

BWe

BWf

BWg

BWh

Input-

synchronous

Byte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM.

Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,

BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf

controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.

WE

Input-

synchronous

Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This

signal must be asserted LOW to initiate a write sequence.

[+] Feedback

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CY7C1474V25-200BGXI Datasheet(PDF) 6 Page - Cypress Semiconductor

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