CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Document Number: 001-00435 Rev. *N

Page 7 of 33

Pin Definitions

Pin Name

I/O

Pin Description

Input-

Synchronous

Data input signals. Sampled on the rising edge of K and K clocks when valid write operations are active.

CY7C1511KV18

− D

[7:0]

CY7C1526KV18

− D

[8:0]

CY7C1513KV18

− D

[17:0]

CY7C1515KV18

− D

[35:0]

WPS

Input-

Synchronous

Write port select

− Active LOW. Sampled on the rising edge of the K clock. When asserted active, a write

Input-

Synchronous

Nibble write select 0, 1

− Active LOW (CY7C1511KV18 Only). Sampled on the rising edge of the K and

K clocks when write operations are active. Used to select which nibble is written into the device during

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

ignores the corresponding nibble of data and it is not written into the device.

Input-

Synchronous

Byte write select 0, 1, 2, and 3

− Active LOW. Sampled on the rising edge of the K and K clocks when

write operations are active. Used to select which byte is written into the device during the current portion

of the write operations. Bytes not written remain unaltered.

CY7C1526KV18

− BWS

CY7C1513KV18

− BWS

CY7C1515KV18

− BWS

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

ignores the corresponding byte of data and it is not written into the device.

A

Input-

Synchronous

Address inputs. Sampled on the rising edge of the K clock during active read and write operations. These

address inputs are multiplexed for both read and write operations. Internally, the device is organized as

8M x 8 (4 arrays each of 2M x 8) for CY7C1511KV18, 8M x 9 (4 arrays each of 2M x 9) for CY7C1526KV18,

4M x 18 (4 arrays each of 1M x 18) for CY7C1513KV18 and 2M x 36 (4 arrays each of 512K x 36) for

CY7C1515KV18. Therefore, only 21 address inputs are needed to access the entire memory array of

CY7C1511KV18 and CY7C1526KV18, 20 address inputs for CY7C1513KV18 and 19 address inputs for

CY7C1515KV18. These inputs are ignored when the appropriate port is deselected.

Outputs-

Synchronous

Data output signals. These pins drive out the requested data when the read operation is active. Valid data

is driven out on the rising edge of the C and C clocks during read operations, or K and K when in single

CY7C1511KV18

− Q

[7:0]

CY7C1526KV18

− Q

[8:0]

CY7C1513KV18

− Q

[17:0]

CY7C1515KV18

− Q

[35:0]

RPS

Input-

Synchronous

Read port select

− Active LOW. Sampled on the rising edge of positive input clock (K). When active, a

read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is

allowed to complete and the output drivers are automatically tristated following the next rising edge of the

C clock. Each read access consists of a burst of four sequential transfers.

C

Input Clock

Positive input clock for output data. C is used in conjunction with C to clock out the read data from the

device. C and C can be used together to deskew the flight times of various devices on the board back to

the controller. See Application Example on page 11 for further details.

C

Input Clock

Negative input clock for output data. C is used in conjunction with C to clock out the read data from the

device. C and C can be used together to deskew the flight times of various devices on the board back to

the controller. See Application Example on page 11 for further details.

K

Input Clock

Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and

K

Input Clock

Negative input clock input. K is used to capture synchronous inputs being presented to the device and to

CQ

Echo Clock

CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for

output data (C) of the QDR II. In the single clock mode, CQ is generated with respect to K. The timings

for the echo clocks are shown in the Switching Characteristics on page 25.

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