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CY7C63743C-QXC Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY7C63743C-QXC Datasheet(HTML) 8 Page - Cypress Semiconductor |
8 / 53 page CY7C63722C CY7C63723C CY7C63743C Document #: 38-08022 Rev. *E Page 8 of 53 Data Memory Organization The CY7C637xxC microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned into four areas: program stack, data stack, user variables and USB endpoint FIFOs as shown below. Figure 2. Data Memory Organization I/O Register Summary I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads the selected port into the accumulator. IOWR writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Note that specifying address 0 with IOWX (e.g., IOWX 0h) means the I/O port is selected solely by the contents of X. Note: All bits of all registers are cleared to all zeros on reset, except the Processor Status and Control Register (Figure 33). All registers not listed are reserved, and should never be written by firmware. All bits marked as reserved should always be written as 0 and be treated as undefined by reads. After reset Address 8-bit DSP 8-bit PSP 0x00 Program Stack Growth (User’s firmware moves DSP) 8-bit DSP User Selected Data Stack Growth User Variables 0xE8 USB FIFO for Address A endpoint 2 0xF0 USB FIFO for Address A endpoint 1 0xF8 USB FIFO for Address A endpoint 0 Top of RAM Memory 0xFF Table 1. I/O Register Summary Register Name I/O Address Read/Write Function Fig Port 0 Data 0x00 R/W GPIO Port 0 7 Port 1 Data 0x01 R/W GPIO Port 1 8 Port 2 Data 0x02 R Auxiliary input register for D+, D–, VREG, XTALIN Port 0 Interrupt Enable 0x04 W Interrupt enable for pins in Port 0 37 Port 1 Interrupt Enable 0x05 W Interrupt enable for pins in Port 1 38 Port 0 Interrupt Polarity 0x06 W Interrupt polarity for pins in Port 0 39 Port 1 Interrupt Polarity 0x07 W Interrupt polarity for pins in Port 1 Port 0 Mode0 0x0A W Controls output configuration for Port 0 9 Port 0 Mode1 0x0B W Port 1 Mode0 0x0C W Controls output configuration for Port 1 11 Port 1 Mode1 0x0D W 12 [+] Feedback |
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