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CY7C67300-100AXA Datasheet(PDF) 4 Page - Cypress Semiconductor |
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CY7C67300-100AXA Datasheet(HTML) 4 Page - Cypress Semiconductor |
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4 / 102 page  CY7C67300 Document #: 38-08015 Rev. *K Page 4 of 102 USB Interface EZ-Host has two built in Host/Peripheral SIEs and four USB transceivers that meet the USB 2.0 specification requirements for full and low speed (high speed is not supported). In Host mode, EZ-Host supports four downstream ports, each support control, interrupt, bulk, and isochronous transfers. In Peripheral mode, EZ-Host supports one peripheral port with eight endpoints for each of the two SIEs. Endpoint 0 is dedicated as the control endpoint and only supports control transfers. Endpoints 1 though 7 support interrupt, bulk (up to 64 bytes/packet), or isochronous transfers (up to 1023 Bytes/packet size). EZ-Host also supports a combination of Host and Peripheral ports simultaneously as shown in Table 3. GPIO10 D10 D10 SCK[1] GPIO9 D9 D9 nSSI[1] GPIO8 D8 D8 MISO[1] GPIO7 D7 D7 GPIO6 D6 D6 GPIO5 D5 D5 GPIO4 D4 D4 GPIO3 D3 D3 GPIO2 D2 D2 GPIO1 D1 D1 GPIO0 D0 D0 Table 1. Interface Options for GPIO Pins (continued) GPIO Pins HPI IDE PWM HSS SPI UART I2C OTG Note 2. Alternate interface location. Table 2. Interface Options for External Memory Bus Pins MEM Pins HPI IDE PWM HSS SPI UART I2C OTG D15 CTS[2] D14 RTS[2] D13 RXD[2] D12 TXD[2] D11 MOSI[2] D10 SCK[2] D9 nSSI[2] D8 MISO[2] D[7:0] A[18:0] CONTROL Table 3. USB Port Configuration Options Port Configurations Port 1A Port 1B Port 2A Port 2B OTG OTG – – – OTG + 2 Hosts OTG – Host Host OTG + 1 Host OTG – Host – OTG + 1 Host OTG – – Host OTG + 1 Peripheral OTG – Peripheral – OTG + 1 Peripheral OTG – – Peripheral 4 Hosts Host Host Host Host 3 Hosts Any Combination of Ports 2 Hosts Any Combination of Ports 1 Host Any Port [+] Feedback |
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