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CY8C3245AXI-158 Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CY8C3245AXI-158
Description  Programmable System-on-Chip (PSoC) DC to 50 MHz operation
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C3245AXI-158 Datasheet(HTML) 6 Page - Cypress Semiconductor

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PSoC® 3: CY8C32 Family
Data Sheet
Document Number: 001-56955 Rev. *K
Page 6 of 120
Figure 2-2. 48-pin QFN Part Pinout[8]
QFN
(Top View)
10
11
12
Vssb
Ind
Vboost
Vbat
35
34
33
32
31
30
29
28
27
26
25
36
1
2
3
4
5
6
7
8
9
Vcca
Vssa
Vdda
P12[2] (SIO)
P12[3] (SIO)
P0[0] (GPIO)
P0[1] (GPIO)
P0[2] (GPIO)
P0[3] (Extref0, GPIO)
(GPIO) P2[6]
(GPIO) P2[7]
(GPIO, nTRST) P1[5]
(GPIO, TDI) P1[4]
(GPIO, TDO, SWV) P1[3]
(GPIO, TCK, SWDCK) P1[1]
(GPIO, TMS, SWDIO) P1[0]
(GPIO, Configurable XRES) P1[2]
P12[1] (SIO, I2C1: SDA)
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
Lines show
Vddio to I/O
supply
association
Notes
7. The center pad on the QFN package should be connected to digital ground (Vssd) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.
8. PPins are Do Not Use (DNU) on devices without USB. The pin must be left floating.


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