CY8C20X36A/46A/66A/96A

Document Number: 001-54459 Rev. *E

Page 10 of 43

30-Ball Part Pinout

Table 4. Pin Definitions – CY8C20766A, CY8C20746A 30-Ball Part Pinout (WLCSP)

Pin No.

Type

Name

Description

Digital

Analog

Figure 5. CY8C20766A 30-Ball WLCSP

A1

IOH

I

P0[2]

Bottom View

Top View

A2

IOH

I

P0[6]

A3

Power

Supply voltage

A4

IOH

I

P0[1]

Integrating Input

A5

I/O

I

P2[7]

B1

I/O

I

P2[6]

B2

IOH

I

P0[0]

B3

IOH

I

P0[4]

B4

IOH

I

P0[3]

Integrating Input

B5

I/O

I

P2[5]

Crystal Output (Xout)

C1

I/O

I

P2[2]

C2

I/O

I

P2[4]

C3

IOH

I

P0[7]

C4

IOH

I

P0[5]

C5

I/O

I

P2[3]

Crystal Input (Xin)

D1

I/O

I

P2[0]

D2

I/O

I

P3[0]

D3

I/O

I

P3[1]

D4

I/O

I

P3[3]

D5

I/O

I

P2[1]

E1

Input

XRES

Active high external reset with

internal pull-down

E2

IOHR

I

P1[6]

E3

IOHR

I

P1[4]

Optional external clock input

(EXT CLK)

E4

IOHR

I

P1[7]

E5

IOHR

I

P1[5]

F1

IOHR

I

P1[2]

F2

IOHR

I

P1[0]

CLK[12]

F3

Power

Supply ground

F4

IOHR

I

P1[1]

MOSI

F5

IOHR

I

P1[3]

SPI CLK

5

432

1

A

B

C

D

E

F

1

234

5

B

C

D

E

F

A

Notes

11. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives

resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive

resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use

alternate pins if you encounter issues.

12. Alternate SPI clock.

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