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CY8C53 Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY8C53 Datasheet(HTML) 9 Page - Cypress Semiconductor |
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9 / 106 page  PRELIMINARY PSoC® 5: CY8C53 Family Datasheet Document Number: 001-66237 Rev. *A Page 9 of 106 Figure 2-4. Example PCB Layout for 100-Pin TQFP Part for Optimal Analog Performance 3. Pin Descriptions IDAC0, IDAC2. Low resistance output pin for high current DACs (IDAC). OpAmp0out, OpAmp2out. High current output of uncommitted opamp[5]. Extref0, Extref1. External reference input to the analog system. OpAmp0-, OpAmp2-. Inverting input to uncommitted opamp. OpAmp0+, OpAmp2+. Noninverting input to uncommitted opamp. GPIO. General purpose I/O pin provides interfaces to the CPU, digital peripherals, analog peripherals, interrupts, LCD segment drive, and CapSense[5]. Ind. Inductor connection to boost pump. kHz XTAL: Xo, kHz XTAL: Xi. 32.768 kHz crystal oscillator pin. MHz XTAL: Xo, MHz XTAL: Xi. 4 to 25 MHz crystal oscillator pin. If a crystal is not used then Xi must be shorted to ground and Xo must be left floating. SIO. Special I/O provides interfaces to the CPU, digital peripherals and interrupts with a programmable high threshold voltage, analog comparator, high sink current, and high impedance state when the device is unpowered. SWDCK. Serial Wire Debug Clock programming and debug port connection. SWDIO. Serial Wire Debug Input and Output programming and debug port connection. SWV. Single Wire Viewer output. USBIO, D+. Provides D+ connection directly to a USB 2.0 bus. May be used as a digital I/O pin; it is powered from VDDD instead of from a VDDIO. Pins are Do Not Use (DNU) on devices without USB. USBIO, D-. Provides D- connection directly to a USB 2.0 bus. May be used as a digital I/O pin; it is powered from VDDD instead of from a VDDIO. Pins are DNU on devices without USB. VBOOST. Power sense connection to boost pump. VBAT. Battery supply to boost pump. VCCA. Output of analog core regulator and input to analog core. Requires a 1 µF capacitor to VSSA. Regulator output not for external use. VCCD. Output of digital core regulator and input to digital core. The two VCCD pins must be shorted together, with the trace between them as short as possible, and a 1 µF capacitor to VSSD; see Power System on page 22. Regulator output not for external use. VDDA. Supply for all analog peripherals and analog core regulator. VDDA must be the highest voltage present on the device. All other supply pins must be less than or equal to VDDA. VDDD. Supply for all digital peripherals and digital core regulator. VDDD must be less than or equal to VDDA. VSSA. Ground for all analog peripherals. VSSB. Ground connection for boost pump. VSSD. Ground for all digital logic and I/O pins. VDDIO0, VDDIO1, VDDIO2, VDDIO3. Supply for I/O pins. Each VDDIO must be tied to a valid operating voltage (2.7 V to 5.5 V), and must be less than or equal to VDDA. XRES. External reset pin. Active low with internal pull-up. Vddd Vssd Vdda Vssa Vssd Plane Vssa Plane Note 5. GPIOs with opamp outputs are not recommended for use with CapSense [+] Feedback |
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