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CY8C20234 Datasheet(PDF) 3 Page - Cypress Semiconductor |
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CY8C20234 Datasheet(HTML) 3 Page - Cypress Semiconductor |
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3 / 47 page  CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 Document Number: 001-05356 Rev. *O Page 3 of 47 PSoC Functional Overview The PSoC family consists of many Programmable System-on-Chips with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU based system components with one low cost single chip programmable component. A PSoC device includes configurable analog and digital blocks and programmable interconnect. This architecture enables the user to create customized peripheral configurations to match the requirements of each individual application. Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The PSoC architecture for this device family, as shown in Figure 1, consists of three main areas: the Core, the System Resources, and the CapSense Analog System. A common versatile bus enables connection between I/O and the analog system. Each CY8C20x34 PSoC device includes a dedicated CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. Depending on the PSoC package, up to 28 general purpose I/O (GPIO) are also included. The GPIO provide access to the MCU and analog mux. PSoC Core The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, IMO , and ILO. The CPU core, called the M8C, is a powerful processor with speeds up to 12 MHz. The M8C is a two MIPS, 8-bit Harvard-architecture microprocessor. System Resources provide additional capability such as a configurable I2C slave or SPI master-slave communication interface and various system resets supported by the M8C. The Analog System consists of the CapSense PSoC block and an internal 1.8 V analog reference. Together they support capac- itive sensing of up to 28 inputs. CapSense Analog System The Analog System contains the capacitive sensing hardware. Several hardware algorithms are supported. This hardware performs capacitive sensing and scanning without requiring external components. Capacitive sensing is configurable on each GPIO pin. Scanning of enabled CapSense pins is completed quickly and easily across multiple ports. Figure 1. Analog System Block Diagram Analog Multiplexer System The Analog Mux Bus connects to every GPIO pin. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with the CapSense block comparator. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include: ■ Complex capacitive sensing interfaces such as sliders and touch pads ■ Chip-wide mux that enables analog input from any I/O pin ■ Crosspoint connection between any I/O pin combinations ID AC Referenc e Buffer Vr C internal C ap Sens e C ounters C om parator Mu x Mu x Refs C apSens e Cloc k Select Relaxation O s c illator (RO) CSCLK IMO [+] Feedback |
Similar Part No. - CY8C20234 |
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Similar Description - CY8C20234 |
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