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CY8C28XXX Datasheet(PDF) 10 Page - Cypress Semiconductor

Part # CY8C28XXX
Description  PSoC Programmable System-on-Chip Low power at high speed
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C28XXX Datasheet(HTML) 10 Page - Cypress Semiconductor

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CY8C24094, CY8C24794
CY8C24894, CY8C24994
Document Number: 38-12018 Rev. *Z
Page 10 of 59
8.3 68-Pin Part Pinout
The following 68-pin QFN part table and drawing is for the CY8C24994 PSoC device.
Table 4. 68-Pin Part Pinout (QFN[7])
Pin
No.
Type
Name
Description
Figure 5. CY8C24994 68-Pin PSoC Device
Digital Analog
1
I/O
M
P4[7]
2
I/O
M
P4[5]
3
I/O
MP4[3]
4
I/O
MP4[1]
5
NC
No connection
6
NC
No connection
7
Power
VSS
Ground connection
8
I/O
M
P3[7]
9
I/O
M
P3[5]
10
I/O
MP3[3]
11
I/O
MP3[1]
12
I/O
M
P5[7]
13
I/O
M
P5[5]
14
I/O
MP5[3]
15
I/O
MP5[1]
16
I/O
M
P1[7]
I2C SCL
17
I/O
M
P1[5]
I2C SDA
18
I/O
M
P1[3]
19
I/O
M
P1[1]
I2C SCL ISSP SCLK[8]
20
Power
VSS
Ground connection
21
USB
D+
22
USB
D–
23
Power
VDD
Supply voltage
24
I/O
P7[7]
25
I/O
P7[6]
26
I/O
P7[5]
27
I/O
P7[4]
28
I/O
P7[3]
29
I/O
P7[2]
Pin
No.
Type
Name
Description
30
I/O
P7[1]
Digital
Analog
31
I/O
P7[0]
50
I/O
M
P4[6]
32
I/O
M
P1[0]
I2C SDA, ISSP SDATA[8]
51
I/O
I, M
P2[0]
Direct switched capacitor block input
33
I/O
M
P1[2]
52
I/O
I, M
P2[2]
Direct switched capacitor block input
34
I/O
M
P1[4]
Optional EXTCLK
53
I/O
M
P2[4]
External AGND input
35
I/O
M
P1[6]
54
I/O
M
P2[6]
External VREF input
36
I/O
M
P5[0]
55
I/O
I, M
P0[0]
Analog column mux input
37
I/O
M
P5[2]
56
I/O
I, M
P0[2]
Analog column mux input and column output
38
I/O
M
P5[4]
57
I/O
I, M
P0[4]
Analog column mux input and column output
39
I/O
M
P5[6]
58
I/O
I, M
P0[6]
Analog column mux input
40
I/O
M
P3[0]
59
Power
VDD
Supply voltage
41
I/O
M
P3[2]
60
Power
VSS
Ground connection
42
I/O
M
P3[4]
61
I/O
I, M
P0[7]
Analog column mux input, integration input #1
43
I/O
M
P3[6]
62
I/O
I/O, M
P0[5]
Analog column mux input and column output, integration
input #2
44
NC
No connection.
63
I/O
I/O, M
P0[3]
Analog column mux input and column output
45
NC
No connection.
64
I/O
I, M
P0[1]
Analog column mux input
46
Input
XRES
Active high pin reset with internal
pull-down.
65
I/O
M
P2[7]
47
I/O
M
P4[0]
66
I/O
M
P2[5]
48
I/O
M
P4[2]
67
I/O
I, M
P2[3]
Direct switched capacitor block input
49
I/O
M
P4[4]
68
I/O
I, M
P2[1]
Direct switched capacitor block input
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input.
Notes
7. The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it
should be electrically floated and not connected to any other signal.
8. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
NC
NC
Vss
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
NC
NC
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
P1[6], M
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
QFN
(Top View)
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