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CY8CLED03G01 Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CY8CLED03G01 Datasheet(HTML) 10 Page - Cypress Semiconductor |
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10 / 55 page  CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 Document Number: 001-46319 Rev. *N Page 10 of 55 Figure 5-2. Current Waveforms The minimum on-time and off-time circuits in the PowerPSoC prevent oscillations at very high frequencies, which can be very destructive to output switches. 5.2 Low Side N-Channel FETs The internal low side N-Channel FETs are designed to enhance system integration. The low side N-Channel FETs include the following key features: ■ Drive capability up to 1 A ■ Switching times of 20 ns (rise and fall times) to ensure high efficiency (more than 90%) ■ Drain source voltage rating 32 V ■ Low RDS(ON) to ensure high efficiency ■ Switching frequency up to 2 MHz 5.3 External Gate Drivers These gate drivers enable the use of external FETs with higher current capabilities or lower RDS(ON). The external gate drivers directly drive MOSFETs that are used in switching applications. The gate driver provides multiple programmable drive strength steps to enable improved EMI management. The external gate drivers include the following key features: ■ Programmable drive strength options (25%, 50%, 75%, 100%) for EMI management ■ Rise and fall times at 55 ns with 4 nF load 5.4 Dimming Modulation Schemes There are three dimming modulation schemes available with the PowerPSoC. The configurable modulation schemes are: ■ Precise Intensity Signal Modulation (PrISM) ■ Delta Sigma Modulation Mode (DMM) ■ Pulse Width Modulation (PWM) 5.4.1 PrISM Mode Configuration ■ High resolution operation up to 16 bits ■ Dedicated PrISM module enables customers to use core PSoC digital blocks for other needs ■ Clocking up to 48 MHz ■ Selectable output signal density ■ Reduced EMI The PrISM mode compares the output of a pseudo-random counter with a signal density value. The comparator output asserts when the count value is less than or equal to the value in the signal density register. 5.4.2 DMM Mode Configuration ■ High resolution operation up to 16 bits ■ Configurable output frequency and delta sigma modulator width to trade off repeat rates versus resolution ■ Dedicated DMM module enables customers to use PSoC digital blocks for other uses ■ Clocking up to 48 MHz The DMM modulator consists of a 12-bit PWM block and a 4-bit Delta Sigma Modulator (DSM) block. The width of the PWM, the width of the DMM, and the clock defines the output frequency. The duty cycle of the PWM output is dithered by using the DSM block which has a user-selectable resolution up to 4 bits. 5.4.3 PWM Mode Configuration ■ High resolution operation up to 16 bits ■ User programmable period from 1 to 65535 clocks ■ Dedicated PWM module enables customers to use core PSoC digital blocks for other use ■ Interrupt on rising edge of the output or terminal count ■ Precise PWM phase control to manage system current edges ■ Phase synchronization among the four channels ■ PWM output can be aligned to left, right, or center The PWM features a down counter and a pulse width register. A comparator output is asserted when the count value is less than or equal to the value in the pulse width register. 5.5 Current Sense Amplifier The high side current sense amplifiers provide a differential sense capability to sense the voltage across current sense resistors in lighting systems. The current sense amplifier includes the following key features: ■ Operation with high common mode voltage to 32 V ■ High common mode rejection ratio ■ Programmable bandwidth to optimize system noise immunity An off-chip resistor Rsense is used for high side current measurement as shown in Figure 5-3. on page 11. The output of the current sense amplifier goes to the power peripherals analog multiplexer where, you select the hysteretic controller to which ILED DIM ON OFF REF_B REF_A Hyst Out [+] Feedback |
Similar Part No. - CY8CLED03G01 |
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Similar Description - CY8CLED03G01 |
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