CY8C29466-24SXI datasheet(10/61 Pages) CYPRESS

Part #	CY8C29466-24SXI

Description	PSoC Programmable System-on-Chip Low power at high speed

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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10 / 61 page

CY8C29466, CY8C29566

CY8C29666, CY8C29866

Document Number: 38-12013 Rev. *S

Page 10 of 61

48-Pin Part Pinout

Note

5. These are the ISSP pins, which are not High Z at POR. See the PSoC Programmable System-on-Chip Technical Reference Manual for details.

Table 4. 48-Pin Part Pinout (SSOP)

No.

Type

Name

Description

Figure 5. CY8C29666 48-Pin PSoC Device

Digital

Analog

1

I/O

I

P0[7]

Analog column mux input

2

I/O

P0[5]

Analog column mux input and column output

3

I/O

P0[3]

Analog column mux input and column output

4

I/O

I

P0[1]

Analog column mux input

5

I/O

P2[7]

6

I/O

P2[5]

7

I/O

I

P2[3]

Direct switched capacitor block input

8

I/O

I

P2[1]

Direct switched capacitor block input

9

I/O

P4[7]

10

I/O

P4[5]

11

I/O

P4[3]

12

I/O

P4[1]

13

Power

SMP

Switch mode pump (SMP) connection to

external components required

14

I/O

P3[7]

15

I/O

P3[5]

16

I/O

P3[3]

17

I/O

P3[1]

18

I/O

P5[3]

19

I/O

P5[1]

20

I/O

P1[7]

I2C SCL

21

I/O

P1[5]

I2C SDA

22

I/O

P1[3]

23

I/O

P1[1]

Crystal (XTALin), I2C SCL, ISSP-SCLK[5]

24

Power

VSS

Ground connection

25

I/O

P1[0]

Crystal (XTALout), I2C SDA, ISSP-SDATA[5]

26

I/O

P1[2]

27

I/O

P1[4]

Optional EXTCLK

28

I/O

P1[6]

29

I/O

P5[0]

30

I/O

P5[2]

31

I/O

P3[0]

32

I/O

P3[2]

33

I/O

P3[4]

34

I/O

P3[6]

35

Input

XRES

Active high external reset with internal

pull-down

36

I/O

P4[0]

37

I/O

P4[2]

38

I/O

P4[4]

39

I/O

P4[6]

40

I/O

I

P2[0]

Direct switched capacitor block input

41

I/O

I

P2[2]

Direct switched capacitor block input

42

I/O

P2[4]

External Analog Ground (AGND)

43

I/O

P2[6]

External Voltage Reference (VREF)

44

I/O

I

P0[0]

Analog column mux input

45

I/O

P0[2]

Analog column mux input and column output

46

I/O

P0[4]

Analog column mux input and column output

47

I/O

I

P0[6]

Analog column mux input

48

Power

VDD

Supply voltage

LEGEND: A = Analog, I = Input, and O = Output.

SSOP

A, I, P0[7]

VDD

A, IO, P0[5]

P0[6], A, I

A, IO, P0[3]

P0[2], A, IO

A, I, P0[1]

P0[4], A, IO

P2[7]

P0[0], A, I

P2[5]

P2[6], External VREF

A, I, P2[3]

P2[4], External AGND

A, I, P2[1]

P2[2], A, I

P4[7]

P2[0], A, I

P4[5]

P4[6]

P4[3]

P4[4]

P4[1]

P4[2]

SMP

P4[0]

P3[7]

XRES

P3[5]

P3[6]

P3[3]

P3[4]

P3[1]

P3[2]

P5[3]

P3[0]

P5[1]

P5[2]

I2C SCL, P1[7]

P5[0]

I2C SDA, P1[5]

P1[6]

P1[3]

P1[4], EXTCLK

I2C SCL, XTALin, P1[1]

P1[2]

VSS

P1[0], XTALout, I2C SDA

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

43

44

42

40

41

39

38

37

36

35

33

34

32

31

30

29

28

27

26

25

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