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CY8CPLC20-48LFXI Datasheet(PDF) 3 Page - Cypress Semiconductor |
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CY8CPLC20-48LFXI Datasheet(HTML) 3 Page - Cypress Semiconductor |
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3 / 56 page  CY8CPLC20 Document Number: 001-48325 Rev. *J Page 3 of 56 2. PLC Functional Overview The CY8CPLC20 is an integrated powerline communication (PLC) chip with the powerline modem PHY and network protocol stack running on the same device. Apart from the PLC core, the CY8CPLC20 also offers Cypress's revolutionary PSoC technology that enables system designers to integrate multiple functions on the same chip. 2.1 Robust Communication using Cypress’s PLC Solution Powerlines are available everywhere in the world and are a widely available communication medium for PLC technology. The pervasiveness of powerlines also makes it difficult to predict the characteristics and operation of PLC products. Because of the variable quality of powerlines around the world, implementing robust communication has been an engineering challenge for years. The Cypress PLC solution enables secure and reliable communications. Cypress PLC features that enable robust communication over powerlines include: ■ Integrated Powerline PHY modem with optimized filters and amplifiers to work with lossy high voltage and low voltage powerlines. ■ Powerline optimized network protocol that supports bidirec- tional communication with acknowledgement-based signaling. In case of data packet loss due to bursty noise on the powerline, the transmitter has the capability to retransmit data. ■ The powerline network protocol also supports an 8-bit CRC for error detection and data packet retransmission. ■ A Carrier sense multiple access (CSMA) scheme is built into the network protocol that minimizes collisions between packet transmissions on the powerline and supports multiple masters and reliable communication on a bigger network. 2.2 Powerline Modem PHY Figure 2-1. Physical Layer FSK Modem The physical layer of the Cypress PLC solution is implemented using an FSK modem that enables half duplex communication on any high voltage and low voltage powerline. This modem supports raw data rates up to 2400 bps. A block diagram is shown in Figure 2-2 Figure 2-2. Physical Layer FSK Modem Block Diagram 2.2.1 Transmitter Section Digital data from the network layer is serialized by the digital transmitter and fed as input to the modulator. The modulator divides the local oscillator frequency by a definite factor depending on whether the input data is high level logic ‘1’ or low level logic ‘0’. It then generates a square wave at 133.3 kHz (logic ‘0’) or 131.8 kHz (logic ‘1’), which is fed to the Programmable Gain Amplifier to generate FSK modulated signals. This enables tunable amplification of the signal depending on the noise in the channel. The logic ‘1’ frequency can also be configured as 130.4 kHz for wider FSK deviation. 2.2.2 Receiver Section The incoming FSK signal from the powerline is input to a high frequency (HF) band pass filter that filters out-of-band frequency components and outputs a filtered signal within the desired spectrum of 125 kHz to 140 kHz for further demodulation. The mixer block multiplies the filtered FSK signals with a locally generated signal to produce heterodyned frequencies. Powerline Network Protocol Physical Layer FSK Modem Powerline Communication Solution Powerline Transceiver Packet Programmable System Resources Digital and Analog Peripherals PSoC Core Additional System Resources MAC, Decimator, I2C, SPI, UART etc. PLC Core Embedded Application Network Protocol Coupling Circuit HF Band Pass Filter Hysteresis Comparator Digital Receiver IF Band Pass Filter Low Pass Filter Mixer Correlator Modulator Local Oscillator Logic ‘1’ or Logic ‘0’ Square Wave at FSK Frequencies Digital Transmitter Local Oscillator RX Amplifier Programmable Gain Amplifier External Low Pass Filter |
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