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CY14B256P Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY14B256P
Description  256-Kbit (32 K x 8) Serial (SPI) nvSRAM with Real Time Clock
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY14B256P Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY14B256P
Document Number: 001-53881 Rev. *F
Page 7 of 36
SPI Modes
CY14B256P device may be driven by a microcontroller with its
SPI peripheral running in either of these two modes:
■
SPI Mode 0 (CPOL=0, CPHA=0)
■
SPI Mode 3 (CPOL=1, CPHA=1)
For both these modes, the input data is latched in on the rising
edge of SCK starting from the first rising edge after CS goes
active. If the clock starts from a HIGH state (in mode 3), the first
rising edge after the clock toggles is considered. The output data
is available on the falling edge of SCK.
The two SPI modes are shown in Figure 4 and Figure 5. The
status of clock when the bus master is in standby mode and not
transferring data is:
■
SCK remains at 0 for Mode 0
■
SCK remains at 1 for Mode 3
CPOL and CPHA bits must be set in the SPI controller for the
either Mode 0 or Mode 3. CY14B256P detects the SPI mode
from the status of SCK pin when the device is selected by
bringing the CS pin LOW. If SCK pin is LOW when the device is
selected, SPI Mode 0 is assumed and if SCK pin is HIGH,
CY14B256P works in SPI Mode 3.
Figure 3. System Configuration using SPI nvSRAM
P
6
5
2
B
4
1
Y
C
P
6
5
2
B
4
1
Y
C
uC o ntrolle r
SC K
MO S I
MIS O
SI
SO
O
S
I
S
K
C
SS C K
CS
HO L D
HO L D
CS
CS 1
CS 2
HO L D 1
HO L D 2
Figure 4. SPI Mode 0
LSB
MSB
7
654
32
10
CS
SCK
SI
0
1
2
3
4
5
6
7
Figure 5. SPI Mode 3
CS
SCK
SI
7
654
32
10
LSB
MSB
0
1
2
3
4
5
6
7


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