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CY14B064PA Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY14B064PA Datasheet(HTML) 8 Page - Cypress Semiconductor |
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8 / 43 page  CY14C064PA CY14B064PA CY14E064PA Document #: 001-68249 Rev. *A Page 8 of 43 SPI Operating Features Power-Up Power-up is defined as the condition when the power supply is turned on and VCC crosses Vswitch voltage. During this time, the CS must be enabled to follow the VCC voltage. Therefore, CS must be connected to VCC through a suitable pull-up resistor. As a built in safety feature, CS is both edge sensitive and level sensitive. After power-up, the device is not selected until a falling edge is detected on CS. This ensures that CS must have been HIGH before going LOW to start the first operation. As described earlier, nvSRAM performs a Power Up RECALL operation after power-up and, therefore, all memory accesses are disabled for tFA duration after power-up. The HSB pin can be probed to check the Ready/Busy status of nvSRAM after power-up. Power-On Reset A power-on reset (POR) circuit is included to prevent inadvertent writes. At power-up, the device does not respond to any instruction until the VCC reaches the POR threshold voltage (VSWITCH). After VCC transitions the POR threshold, the device is internally reset and performs a Power-Up RECALL operation. During Power Up RECALL all device accesses are inhibited. The device is in the following state after POR: Deselected (after power-up, a falling edge is required on CS before any instructions are started). Standby power mode Not in the Hold condition Status Register state: Write Enable (WEN) bit is reset to ‘0’. WPEN, BP1, BP0 unchanged from previous STORE operation. The WPEN, BP1, and BP0 bits of the Status Register are nonvolatile bits and remain unchanged from the previous STORE operation. Prior to selecting and issuing instructions to the memory, a valid and stable VCC voltage must be applied. This voltage must remain valid until the end of the instruction transmission. Power Down At power-down (continuous decay of VCC), when VCC drops from the normal operating voltage and below the VSWITCH threshold voltage, the device stops responding to any instruction sent to it. If a write cycle is in progress and the last data bit D0 has been received when the power goes down, it is allowed tDELAY time to complete the write. After this, all memory accesses are inhibited and a conditional AutoStore operation is performed (AutoStore is not performed if no writes have happened since the last RECALL cycle). This feature prevents inadvertent writes to nvSRAM from happening during power-down. However, to avoid the possibility of inadvertent writes during power-down, ensure that the device is deselected and is in standby power mode and the CS follows the voltage applied on VCC. Active Power and Standby Power Modes When CS is LOW, the device is selected and is in the active power mode. The device consumes ICC current, as specified in DC Electrical Characteristics on page 32. When CS is HIGH, the device is deselected and the device goes into the standby power mode after tSB time if a STORE or RECALL cycle is not in progress. If a STORE/RECALL cycle is in progress, the device goes into the standby power mode after the STORE/RECALL cycle is completed. In the standby power mode the current drawn by the device drops to ISB. [+] Feedback |
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