CY8C20XX6 datasheet(9/59 Pages) CYPRESS

Part #	CY8C20XX6

Description	PSoC Programmable System-on-Chip Low power at high speed

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY8C24094, CY8C24794

CY8C24894, CY8C24994

Document Number: 38-12018 Rev. *Z

Page 9 of 59

8.2 56-Pin Part Pinout (with XRES)

Table 3. 56-Pin Part Pinout (QFN[6])

No.

Type

Name

Description

Figure 4. CY8C24894 56-Pin PSoC Device

Digital Analog

1

I/O

I, M

P2[3]

Direct switched capacitor block input

2

I/O

I, M

P2[1]

Direct switched capacitor block input

3

I/O

MP4[7]

4

I/O

MP4[5]

5

I/O

MP4[3]

6

I/O

MP4[1]

7

I/O

MP3[7]

8

I/O

MP3[5]

9

I/O

MP3[3]

10

I/O

MP3[1]

11

I/O

M

P5[7]

12

I/O

M

P5[5]

13

I/O

MP5[3]

14

I/O

MP5[1]

15

I/O

M

P1[7]

I2C SCL

16

I/O

M

P1[5]

I2C SDA

17

I/O

M

P1[3]

18

I/O

MP1[1]

I2C SCL, ISSP SCLK[5]

19

Power

VSS

Ground connection

20

USB

D+

21

USB

D–

22

Power

VDD

Supply voltage

23

I/O

P7[7]

24

I/O

P7[0]

25

I/O

M

P1[0]

I2C SDA, ISSP SDATA[5]

26

I/O

M

P1[2]

27

I/O

M

P1[4]

Optional EXTCLK

28

I/O

MP1[6]

29

I/O

MP5[0]

No.

Type

Name

Description

30

I/O

MP5[2]

Digital Analog

31

I/O

M

P5[4]

44

I/O

M

P2[6]

External VREF input

32

I/O

M

P5[6]

45

I/O

I, M

P0[0]

Analog column mux input

33

I/O

MP3[0]

46

I/O

I, M

P0[2]

Analog column mux input

34

I/O

MP3[2]

47

I/O

I, M

P0[4]

Analog column mux input VREF

35

I/O

M

P3[4]

48

I/O

I, M

P0[6]

Analog column mux input

36

Input

XRES Active high external reset with internal

pull-down

49

Power

VDD

Supply voltage

37

I/O

MP4[0]

50

Power

VSS

Ground connection

38

I/O

MP4[2]

51

I/O

I, M

P0[7]

Analog column mux input

39

I/O

M

P4[4]

52

I/O

I/O, M

P0[5]

Analog column mux input and column output

40

I/O

M

P4[6]

53

I/O

I/O, M

P0[3]

Analog column mux input and column output

41

I/O

I, M

P2[0]

Direct switched capacitor block input

54

I/O

I, M

P0[1]

Analog column mux input

42

I/O

I, M

P2[2]

Direct switched capacitor block input

55

I/O

M

P2[7]

43

I/O

M

P2[4]

External AGND input

56

I/O

MP2[5]

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.

QFN

(Top Vie w)

A, I, M, P2[3]

A, I, M, P2[1]

M, P4[7]

M, P4[5]

M, P4[3]

M, P4[1]

M, P3[7]

M, P3[5]

M, P3[3]

M, P3[1]

M, P5[7]

M, P5[5]

M, P5[3]

M, P5[1]

1

2

3

4

5

6

7

8

9

10

11

12

13

14

P2[2], A, I, M

P2[0], A, I, M

P4[6], M

P4[4], M

P4[2], M

P4[0], M

XRES

P3[4], M

P3[2], M

P3[0], M

P5[6], M

P5[4], M

P5[2], M

P5[0], M

42

41

40

39

38

37

36

35

34

33

32

31

30

29

Notes

5. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.

6. The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it

should be electrically floated and not connected to any other signal.

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