CY14B256Q2A-SXIT datasheet(5/33 Pages) CYPRESS

Part #	CY14B256Q2A-SXIT

Description	256-Kbit (32 K x 8) SPI nvSRAM Infinite read, write, and RECALL cycles

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Manufacturer	CYPRESS [Cypress Semiconductor]

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CY14C256Q

CY14B256Q

CY14E256Q

Document #: 001-65282 Rev. *B

Page 5 of 33

AutoStore Operation

The AutoStore operation is a unique feature of nvSRAM which

automatically stores the SRAM data to QuantumTrap cells

during power-down. This STORE makes use of an external

capacitor (VCAP) and enables the device to safely STORE the

data in the nonvolatile memory when power goes down.

During normal operation, the device draws current from VCC to

charge the capacitor connected to the VCAP pin. When the

voltage on the VCC pin drops below VSWITCH during power-down,

the device inhibits all memory accesses to nvSRAM and

automatically performs a conditional STORE operation using the

charge from the VCAP capacitor. The AutoStore operation is not

initiated if no write cycle has been performed since last RECALL.

Note If a capacitor is not connected to VCAP pin, AutoStore must

be disabled by issuing the AutoStore Disable instruction

(AutoStore Disable (ASDISB) Instruction on page 15). If

AutoStore is enabled without a capacitor on the VCAP pin, the

device attempts an AutoStore operation without sufficient charge

to complete the STORE. This will corrupt the data stored in

nvSRAM, Status Register as well as the serial number and it will

unlock the SNL bit. To resume normal functionality, the WRSR

instruction must be issued to update the nonvolatile bits BP0,

BP1, and WPEN in the Status Register.

Figure 3 shows the proper connection of the storage capacitor

(VCAP) for AutoStore operation. Refer to DC Electrical

Characteristics on page 21 for the size of the VCAP.

Note CY14X256Q1A does not support AutoStore operation. You

must perform Software STORE operation by using the SPI

STORE instruction to secure the data.

Figure 3. AutoStore Mode

Software STORE Operation

Software STORE enables the user to trigger a STORE operation

through a special SPI instruction. STORE operation is initiated

by executing STORE instruction irrespective of whether a write

has been performed since the last NV operation.

A STORE cycle takes tSTORE time to complete, during which all

the memory accesses to nvSRAM are inhibited. The RDY bit of

the Status Register or the HSB pin may be polled to find the

Ready or Busy status of the nvSRAM. After the tSTORE cycle time

is completed, the SRAM is activated again for read and write

operations.

Hardware STORE and HSB pin Operation

The HSB pin in CY14X256Q3A is used to control and

acknowledge STORE operations. If no STORE or RECALL is in

progress, this pin can be used to request a Hardware STORE

cycle. When the HSB pin is driven LOW, nvSRAM conditionally

initiates a STORE operation after tDELAY duration. A STORE

cycle starts only if a write to the SRAM has been performed since

the last STORE or RECALL cycle. Reads and Writes to the

memory are inhibited for tSTORE duration or as long as HSB pin

is LOW. The HSB pin also acts as an open drain driver (internal

100 k

 weak pull-up resistor) that is internally driven LOW to

indicate a busy condition when the STORE (initiated by any

means) is in progress.

Note After each Hardware and Software STORE operation HSB

is driven HIGH for a short time (tHHHD) with standard output high

current and then remains HIGH by an internal 100 k

 pull-up

resistor.

Note For successful last data byte STORE, a hardware STORE

should be initiated at least one clock cycle after the last data bit

D0 is received.

Upon completion of the STORE operation, the nvSRAM memory

access is inhibited for tLZHSB time after HSB pin returns HIGH.

The HSB pin must be left unconnected if not used.

Note CY14X256Q1A/CY14X256Q2A do not have HSB pin. RDY

bit of the SPI Status Register may be probed to determine the

Ready or Busy status of nvSRAM.

RECALL Operation

A RECALL operation transfers the data stored in the nonvolatile

QuantumTrap elements to the SRAM. A RECALL may be

initiated in two ways: Hardware RECALL, initiated on power-up

and Software RECALL, initiated by a SPI RECALL instruction.

Internally, RECALL is a two step procedure. First, the SRAM data

is cleared. Next, the nonvolatile information is transferred into the

SRAM cells. All memory accesses are inhibited while a RECALL

cycle is in progress. The RECALL operation does not alter the

data in the nonvolatile elements.

Hardware RECALL (Power-Up)

During power-up, when VCC crosses VSWITCH, an automatic

RECALL sequence is initiated, which transfers the content of

nonvolatile memory on to the SRAM. The data would previously

have been stored on the nonvolatile memory through a STORE

sequence.

A Power-Up RECALL cycle takes tFA time to complete and the

memory access is disabled during this time. HSB pin is used to

detect the ready status of the device.

Software RECALL

Software RECALL allows you to initiate a RECALL operation to

restore the content of nonvolatile memory on to the SRAM. A

Software RECALL is issued by using the SPI instruction for

RECALL.

A Software RECALL takes tRECALL time to complete during

which all memory accesses to nvSRAM are inhibited. The

0.1 uF

VCC

VCAP

CS

VCAP

VSS

VCC

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