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CY14V101NA-BA25XI Datasheet(PDF) 11 Page - Cypress Semiconductor |
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CY14V101NA-BA25XI Datasheet(HTML) 11 Page - Cypress Semiconductor |
11 / 22 page CY14V101LA CY14V101NA Document #: 001-53953 Rev. *H Page 11 of 22 AC Switching Characteristics Over the Operating Range Parameters [15] Description 25 ns 45 ns Unit Cypress Parameters Alt Parameters Min Max Min Max SRAM Read Cycle tACE tACS Chip enable access time – 25 – 45 ns tRC[16] tRC Read cycle time 25–45– ns tAA[17] tAA Address access time – 25 – 45 ns tDOE tOE Output enable to data valid – 12 – 20 ns tOHA[17] tOH Output hold after address change 3 – 3 – ns tLZCE[18, 19] tLZ Chip enable to output active 3 – 3 – ns tHZCE[18, 19] tHZ Chip disable to output inactive – 10 – 15 ns tLZOE[18, 19] tOLZ Output enable to output active 0 – 0 – ns tHZOE[18, 19] tOHZ Output disable to output inactive – 10 – 15 ns tPU[18] tPA Chip enable to power active 0 – 0 – ns tPD[18] tPS Chip disable to power standby – 25 – 45 ns tDBE[[18] – Byte enable to data valid – 12 – 20 ns tLZBE[18] – Byte enable to output active 0 – 0 – ns tHZBE[18] – Byte disable to output inactive – 10 – 15 ns SRAM Write Cycle tWC tWC Write cycle time 25 – 45 – ns tPWE tWP Write pulse width 20 – 30 – ns tSCE tCW Chip enable to end of write 20 – 30 – ns tSD tDW Data setup to end of write 10 – 15 – ns tHD tDH Data hold after end of write 0 – 0 – ns tAW tAW Address setup to end of write 20 – 30 – ns tSA tAS Address setup to start of write 0 – 0 – ns tHA tWR Address hold after end of write 0 – 0 – ns tHZWE[18, 19, 20] tWZ Write enable to output disable – 10 – 15 ns tLZWE[18, 19] tOW Output active after end of write 3 – 3 – ns tBW – Byte enable to end of write 20 – 30 – ns Switching Waveforms Figure 4. SRAM Read Cycle #1 (Address Controlled) [16, 17, 21] Address Data Output Address Valid Previous Data Valid Output Data Valid t RC t AA t OHA Notes 15. Test conditions assume signal transition time of 1.8 ns or less, timing reference levels of VCCQ/2, input pulse levels of 0 to VCC Q(typ), and output loading of the specified IOL/IOH and load capacitance shown in Figure 3 on page 10. 16. WE must be HIGH during SRAM read cycles. 17. Device is continuously selected with CE, OE and BHE / BLE LOW. 18. These parameters are guaranteed by design and are not tested. 19. Measured ±200 mV from steady state output voltage. 20. If WE is low when CE goes low, the outputs remain in the high-impedance state. 21. HSB must remain HIGH during READ and WRITE cycles. [+] Feedback |
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