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CY14V104LA-BA25XI Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # CY14V104LA-BA25XI
Description  4-Mbit (512 K x 8 / 256 K x 16) nvSRAM 25 ns and 45 ns access times
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY14V104LA-BA25XI Datasheet(HTML) 3 Page - Cypress Semiconductor

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CY14V104LA
CY14V104NA
Document #: 001-53954 Rev. *F
Page 3 of 22
Pinouts
Figure 1. Pin Diagram – 48-ball FBGA
WE
VCCQ
A11
A10
VCAP
A6
A0
A3
CE
NC
NC
DQ0
A4
A5
NC
DQ2
DQ3
NC
VSS
A9
A8
OE
VSS
A7
NC
NC
VCC
A17
A2
A1
NC
VCCQ
DQ4
NC
DQ5
DQ6
NC
DQ7
NC
A15
A14
A13
A
12
HSB
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A16
A18
NC
DQ1
Top View
(× 8)
[4]
WE
VCCQ
A11
A10
VCAP
A6
A0
A3
CE
DQ10
DQ8
DQ9
A4
A5
DQ13
DQ12
DQ14
DQ15
VSS
A9
A8
OE
VSS
A7
DQ0
BHE
VCC
A17
A2
A1
BLE
VCCQ
DQ2
DQ1
DQ3
DQ4
DQ5 DQ6
DQ7
A15
A14
A13
A
12
HSB
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A16
NC
NC
DQ11
(not to scale)
Top View
(× 16)
[4]
(not to scale)
Pin Definitions
Pin Name
I/O Type
Description
A0–A18
Input
Address Inputs Used to Select One of the 524,288 bytes of the nvSRAM for × 8 Configuration.
A0–A17
Address Inputs Used to Select One of the 262,144 words of the nvSRAM for × 16 Configuration.
DQ0–DQ7 Input/output
Bidirectional Data I/O Lines for × 8 Configuration. Used as input or output lines depending on operation.
DQ0–DQ15
Bidirectional Data I/O Lines for × 16 Configuration. Used as input or output lines depending on operation.
WE
Input
Write Enable Input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
CE
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
I/O pins are tri-stated on deasserting OE HIGH.
BHE
Input
Byte High Enable, Active LOW. Controls DQ15–DQ8.
BLE
Input
Byte Low Enable, Active LOW. Controls DQ7–DQ0.
VSS
Ground
Ground for the Device. Must be connected to the ground of the system.
VCC
Power supply Power Supply Inputs to the Core of the Device.
VCCQ
Power supply Power Supply Inputs for the Inputs and Outputs of the Device.
HSB
Input/output
Hardware Store Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a non-volatile STORE operation. After each Hardware
and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (External pull-up resistor connection
optional).
VCAP
Power supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
non-volatile elements.
NC
No Connect
No Connect. This pin is not connected to the die.
Note
4. Address expansion for 8-Mbit. NC pin not connected to die.
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