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CY2545 Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY2545 Datasheet(HTML) 5 Page - Cypress Semiconductor |
5 / 17 page CY2545, CY2547 Document #: 001-13196 Rev. *C Page 5 of 17 General Description Four Configurable PLLs The CY2545 and CY2547 have four I2C programmable PLLs available to generate output frequencies ranging from 3 to 166 MHz. The advantage of having four PLLs is that a single device generates up to four independent frequencies from a single crystal. Two sets of frequencies for each PLL can be programmed. This enables in system frequency switching using multifunction frequency select pin, FS. I2C Programming The CY2545 and CY2547 have a serial I2C interface that programs the configuration memory array to synthesize output frequencies by programmable output divider, spread character- istics, drive strength, and crystal load capacitance. I2C can also be used for in system control of these programmable features. Input Reference Clocks The input to the CY2545 and CY2547 is either a crystal or a clock signal. The input frequency range for crystals is 8 MHz to 48 MHz. There is provision for two reference clock inputs, CLKIN and EXCLKIN with frequency range of 8 MHz to 166 MHz. For both devices, when CLKIN signal at pin 21 is used as a reference input, a valid signal at EXCLKIN (as specified in the AC and DC Electrical Specification table), must be present for the devices to operate properly. Multiple Power Supplies The CY2545 and CY2547 are designed to operate at internal core supply voltage of 1.8 V. In the case of the high voltage part (CY2545), an internal regulator is used to generate 1.8 V from the 2.5 V/3.0 V/3.3 V VDD supply voltage at pin 22. For the low voltage part (CY2547), this internal regulator is bypassed and 1.8 V at VDD pin 22 is directly used. Output Bank Settings These devices have eight clock outputs grouped in three output driver banks. The Bank 1, Bank 2, and Bank 3 correspond to (CLK1, CLK2), (CLK3, CLK4, CLK5), and (CLK6, CLK7, CLK8), respectively. Separate power supplies are used for each of these banks and they can be any of 2.5 V, 3.0 V, or 3.3 V for CY2545 and 1.8 V for CY2547 giving user multiple choice of output clock voltage levels. Output Source Selection These devices have eight clock outputs (CLK1 - 8). There are six available clock sources for these outputs. These clock sources are: XIN/EXCLKIN, CLKIN, PLL1, PLL2, PLL3, or PLL4. Output clock source selection is done using four out of six crossbar switch. Thus, any one of these six available clock sources can be arbitrarily selected for the clock outputs. This gives user a flexibility to have up to four independent clock outputs. Spread Spectrum Control Two of the four PLLs (PLL3 and PLL4) have spread spectrum capability for EMI reduction in the system. The device uses a Cypress proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the PLL. The spread spectrum feature can be turned on or off using a multifunction control pin (CLK7/SSON). It can be programmed to either center spread range from ±0.125% to ±2.50% or down spread range from –0.25% to –5.0% with Lexmark or Linear profile. Frequency Select The device can store two different PLL frequency configurations, output source selection and output divider values for all eight outputs in its nonvolatile memory location. There is a multi- function programmable pin, CLK3/FS which, if programmed as frequency select input, can be used to select between these two arbitrarily programmed settings. Glitch-Free Frequency Switch When the frequency select pin (FS) is used to switch frequency, the outputs are glitch-free provided frequency is switched using output dividers. This feature enables uninterrupted system operation while clock frequency is switched. Device Reset Function There is a multifunction CLKIN/RST (pin 21) that can be programmed to use for the device reset function. There are two different programmable modes of operation for this device reset function. First one (called POR like reset), when used brings the device in the default register settings loosing all configuration changes made through the I2C interface. The second (called Clean Start), keeps the I2C programmed values while giving all outputs a simultaneous clean start from its low pull-down state. 21 CLKIN/RST Input/Input Multifunction programmable pin: High true reset input or 1.8 V external low voltage reference clock input 22 VDD Power Power supply for core and inputs: 1.8 V 23 XOUT Output Crystal output 24 XIN/EXCLKIN Input Crystal input or 1.8 V external clock input Table 2. Pin Definition – CY2547 24-pin QFN (VDD = 1.8 V Supply) (continued) Pin Number Name I/O Description [+] Feedback |
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