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CY22150KFZXC Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY22150KFZXC Datasheet(HTML) 9 Page - Cypress Semiconductor |
9 / 18 page CY22150 Document #: 38-07104 Rev. *K Page 9 of 18 I2C Interface Timing The CY22150 uses a two-wire I2C-interface that operates up to 400 kbits/second in Read or Write mode. The basic Write serial format is as follows. Start Bit; seven-bit Device Address (DA); R/W Bit; Slave Clock Acknowledge (ACK); eight-bit Memory Address (MA); ACK; eight-bit data; ACK; eight-bit data in MA + 1 if desired; ACK; eight-bit data in MA+2; ACK; and so on until STOP bit.The basic serial format is illustrated in Figure 4 on page 9. Data Valid Data is valid when the Clock is HIGH, and may only be transi- tioned when the clock is LOW, as illustrated in Figure 3. Data Frame Every new data frame is indicated by a start and stop sequence, as illustrated in Figure 5 on page 10. Start Sequence – Start frame is indicated by SDAT going LOW when SCLK is HIGH. Every time a Start signal is given, the next eight-bit data must be the device address (seven bits) and a R/W bit, followed by register address (eight bits) and register data (eight bits). Stop Sequence – Stop frame is indicated by SDAT going HIGH when SCLK is HIGH. A Stop frame frees the bus for writing to another part on the same bus or writing to another random register address. Acknowledge Pulse During Write mode, the CY22150 responds with an ACK pulse after every eight bits. This is accomplished by pulling the SDAT line LOW during the N*9th clock cycle, as illustrated in Figure 6 on page 10. (N = the number of eight-bit segments transmitted.) During Read mode, the ACK pulse after the data packet is sent is generated by the master . Figure 3. Data Valid and Data Transition Periods SDAT SCLK Data valid Transition to next bit CLKLOW CLKHIGH VIH VIL tSU tDH Figure 4. Data Frame Architecture SDAT Write Start Signal Device Address 7-bit R/W = 0 1-bit 8-bit Register Address Slave 1-bit ACK Slave 1-bit ACK 8-bit Register Data Stop Signal Multiple Contiguous Registers Slave 1-bit ACK 8-bit Register Data (XXH) (XXH) (XXH+1) Slave 1-bit ACK 8-bit Register Data (XXH+2) Slave 1-bit ACK 8-bit Register Data (FFH) Slave 1-bit ACK 8-bit Register Data (00H) Slave 1-bit ACK Slave 1-bit ACK SDAT Read Start Signal Device Address 7-bit R/W = 0 1-bit 8-bit Register Address Slave 1-bit ACK Slave 1-bit ACK 7-Bit Device Stop Signal Multiple Contiguous Registers 1-bit R/W = 1 8-bit Register Data (XXH) Address (XXH) Master 1-bit ACK 8-bit Register Data (XXH+1) Master 1-bit ACK 8-bit Register Data (FFH) Master 1-bit ACK 8-bit Register Data (00H) Master 1-bit ACK Master 1-bit ACK [+] Feedback |
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