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CY22381FXCT Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY22381FXCT Datasheet(HTML) 6 Page - Cypress Semiconductor |
6 / 11 page CY22381 CY223811 Document #: 38-07012 Rev. *I Page 6 of 11 IDD Total power supply current 3.3 V Power supply; 3 outputs at 50 MHz – 35 – mA 3.3 V Power supply; 3 outputs at 166 MHz – 70 – mA IDDS Total power supply current in shutdown mode Shutdown active – 5 20 A Switching Characteristics Parameter Name Description Min Typ. Max Unit 1/t1 Output frequency[3, 5] Clock output limit,commercial – – 200 MHz Clock output limit, industrial – – 166 MHz t2 Output duty cycle[3, 6] Duty cycle for outputs, defined as t2 t1, Fout < 100 MHz, divider >= 2, measured at VDD/2 45% 50% 55% Duty cycle for outputs, defined as t2 t1, Fout > 100 MHz or divider = 1, measured at VDD/2 40% 50% 60% t3 Rising edge slew rate[3] Output clock rise time, 20% to 80% of VDD 0.75 1.4 – V/ns t4 Falling edge slew rate[3] Output clock fall time, 20% to 80% of VDD 0.75 1.4 – V/ns t5 Output three-state timing[3] Time for output to enter or leave three-state mode after SHUTDOWN/OE switches – 150 300 ns t6 Clock jitter[3, 7] Peak-to-peak period jitter, CLK outputs measured at VDD/2 –200 – ps t7 Lock time[3] PLL Lock Time from Power up – 1.0 3 ms Switching Waveforms Electrical Characteristics Parameter Description Conditions[1] Min Typ Max Unit Notes 4. Guaranteed by design, not 100% tested. 5. Guaranteed to meet 20% – 80% output thresholds and duty cycle specifications. 6. Reference Output duty cycle depends on XTALIN duty cycle. 7. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate. t1 OUTPUT t2 t3 t4 Figure 2. All Outputs, Duty Cycle and Rise and Fall Time t5 OE ALL OUTPUTS t5 THREE-STATE Figure 3. Output Three-State Timing [+] Feedback |
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