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CY25568 Datasheet(PDF) 7 Page - Cypress Semiconductor |
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CY25568 Datasheet(HTML) 7 Page - Cypress Semiconductor |
7 / 14 page CY25568 Document Number: 38-07111 Rev. *D Page 7 of 14 Power-down (PD#) CY25568 includes a Power-down (PD#, Pin 10) function. This input uses standard 2-Level CMOS logic and is internally pulled up to VDD (HIGH). Connect this pin to GND if power is to be turned off. Modulation Rate Spread Spectrum Clock Generators use frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (fmax) and minimum frequency of the clock (fmin) determine this band of frequencies. The time required to transition from fmin to fmax and back to fmin is the period of the Modulation Rate, Tmod. The Modulation Rate of SSCG clocks are generally referred to in terms of frequency or fmod = 1/Tmod. The input clock frequency, fin, and the internal divider determine the modulation rate. In the case of CY25568, the (spread spectrum) modulation rate is given by the following formula: fmod = fin/DR Where; fmod is the modulation rate, fin is the Input Frequency and DR is the divider ratio as given in Table 4. Notice that Input frequency range is set by FRSEL. Table 4. Modulation Rate FRSEL INPUT FREQUENCY RANGE (MHz) DIVIDER RATIO (DR) 0 4 to 8 128 1 8 to 16 256 M 16 to 32 512 |
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