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CY25568SXCT Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY25568SXCT Datasheet(HTML) 5 Page - Cypress Semiconductor |
5 / 14 page CY25568 Document Number: 38-07111 Rev. *D Page 5 of 14 Input Frequency Range and Selection The CY25568 input frequency range is 4 to 32 MHz. This range is divided into 3 segments and controlled by 3-Level FRSEL pin as given in Table 1. Output Clocks The CY25568 provides 4 separate output clocks, REFOUT, SSCLK1, SSCLK2 and SSCLK3, for use in a wide variety of applications.Each clock output is described in detail. REFOUT REFOUT is a 3.3 volt CMOS level non-modulated copy of the clock at XIN/CLKIN. SSCLK1, 2 and 3 SSCLK1, SSCLK2 and SSCLK3 are Spread Spectrum clock outputs used for the purpose of reducing EMI in digital systems. Each clock can drive separate nets with a capacitive load of up to 20 pF. The frequency function of these clock outputs are selected by using 3-Level D0 and D1 digital inputs and are given in Table 2. REF is the same non-modulated frequency as the input clock. 1x, 2x, or 4x are modulated and multiplied (in the case of 2x and 4x) frequency of the input clock. CCJ3 Cycle-to-cycle jitter - 100 150 ps Fin=32 MHz (refer to Figure 4A) Table 1. Input Frequency Selection FRSEL INPUT FREQUENCY RANGE 0 4.0 to 8.0 MHz 1 8.0 to 16.0 MHz M 16.0 to 32.0 MHz Table 2. Output Clocks Function Selection D0 D1 REFOUT SSCLK1 SSCLK2 SSCLK3 0 0 REF REF 1x 1x 0M REF 1x 2x 2x 0 1 REF REF 2x 2x M 0 REF REF 1x 2x M M REF REF REF REF M 1 REF REF 2x 4x 1 0 REF REF 4x 4x 1M REF 1x 2x 4x 11 REF 1x 2x 4x Timing Electrical Characteristics Test Conditions: VDD=3.3 V, T=25 C, CL=15pF. Rise/Fall time at 0.4 and 2.4 V, duty cycle at 1.5 V |
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