CY25819

Document #: 38-07362 Rev. *D

Page 3 of 13

2

1

3

4

8

7

6

5

XIN/CLKIN

Vss

S0

SSCLK

XOUT

Vdd

PD#

REFCLK

CY25818

CY25819

8-pin SOIC

Pin Configuration

Pin Description

Pin

Name

Description

1

XIN/CLK Clock, Crystal, or Ceramic Resonator Input Pin.

2

Vss

Power Supply Ground.

3S0

Digital Spread% Control Pin. 3-Level input (H-M-L). Default = M.

4

SSCLK

Modulated Spread Spectrum Output Clock. The output frequency is referenced to input frequency. Refer to

Table 2 on page 4 for the amount of modulation (Spread%).

5REFCLK

Unmodulated Reference Clock Output. The unmodulated output frequency is the same as the input

frequency.

6PD#

Power Down Control Pin. Default = H (Vdd).

7

Vdd

Positive Power Supply.

8XOUT

Clock, Crystal, or Ceramic Resonator Output Pin. Leave this pin unconnected if an external clock is used

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