CY29940

Document #: 38-07283 Rev. *E

Page 4 of 10

AC Parameters[8]

Parameter

Description

Conditions

Min

Typ

Max

Unit

Input Frequency

–

–

–

200

MHz

PECL_CLK to Q Delay[9, 10, 11]

2.0

–

3.2

ns

2.1

–

3.4

1.9

–

3.1

2.0

–

3.2

2.5

–

5.2

2.6

–

5

2.5

–

5

2.6

–

5

LVCMOS to Q Delay[9, 10, 11]

 150 MHz

1.9

–

3

ns

2.0

–

3.2

1.8

–

2.9

1.8

–

3.1

2.5

–

4

2.5

–

4

2.3

–

3.8

2.3

–

3.8

Total Jitter

–

–

10

ps

FoutDC

Output Duty Cycle[9, 10, 12]

FCLK < 134 MHz

–

–

55

%

FCLK > 134 MHz

–

–

60

Output-to-Output Skew[9, 10]

–

60

150

ps

–

–

200

Part-to-Part Skew[13]

–

–

1.4

ns

–

–

2.2

Part-to-Part Skew[13]

–

–

1.2

ns

–

–

1.7

Part to Part Skew[14]

PECL_CLK

–

–

850

ps

TCLK

–

–

750

Output Clocks Rise/Fall Time[9, 10]

0.3

–

1.1

ns

0.3

–

1.2

Notes

8. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.

9. Outputs driving 50

transmission lines.

10. See Figure 1 on page 5 and Figure 2 on page 5.

11. Parameters tested @ 150 MHz.

12. 50% input duty cycle.

13. Across temperature and voltage ranges, includes output skew.

14. For a specific temperature and voltage, includes output skew.

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