CY29972

Document #: 38-07290 Rev. *D

Page 4 of 13

5, 26, 27

FB_SEL(2:0)

–

I

PU

Feedback select inputs. These inputs select the divide ratio at

FB_OUT output. See Table 1 on page 1.

52

VCO_SEL

–

I

PU

VCO divider select input. When set LOW, the VCO output is divided

by 2. When set HIGH, the divider is bypassed. See Table 1 on page 1.

31

FB_IN

–

I

PU

Feedback clock input. Connect to FB_OUT for accessing the PLL.

6

PLL_EN

–

I

PU

PLL enable input. When asserted HIGH, PLL is enabled; when LOW,

PLL is bypassed.

7

REF_SEL

–

I

PU

Reference select input. When HIGH, the crystal oscillator is selected;

when LOW, TCLK (0,1) is the reference clock.

8

TCLK_SEL

–

I

PU

TCLK select input. When LOW, TCLK0 is selected and when HIGH

TCLK1 is selected.

2

MR#/OE

–

I

PU

Master reset/output enable input. When asserted LOW, resets all of

the internal flip-flops and also disables all of the outputs. When pulled

high, releases the internal flip-flops from reset and enables all of the

outputs.

14

INV_CLK

–

I

PU

Inverted clock input. When set HIGH, QC(2,3) outputs are inverted.

When set LOW, the inverter is bypassed.

–I

PU

Serial clock input. Clocks data at SDATA into the internal register.

–I

PU

Serial data input. Input data is clocked to the internal register to

enable/disable individual outputs. This provides flexibility in power

management.

17, 22, 28,

33,37, 45, 49

–

–

–

3.3 V power supply for output clock buffers.

13

–

–

–

3.3 V power supply for PLL.

1, 15, 24, 30,

35, 39, 47, 51

–

–

–

Common ground.

Pin

Name

PWR

I/O

Type

Description

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