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CY29972 Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY29972 Datasheet(HTML) 5 Page - Cypress Semiconductor |
5 / 13 page CY29972 Document #: 38-07290 Rev. *D Page 5 of 13 Description The CY29972 has an integrated PLL that provides low skew and low jitter clock outputs for high-performance microprocessors. Three independent banks of four outputs and an independent PLL feedback output (FB_OUT) provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz and 480 MHz. This allows a wide range of output frequencies up to125 MHz. The phase detector compares the input reference clock to the external feedback input. For normal operation, the external feedback input (FB_IN) is connected to the feedback output (FB_OUT). The internal VCO is running at multiples of the input reference clock set by FB_SEL(0:2) and VCO_SEL select inputs (refer to Frequency Table). The VCO frequency is then divided to provide the required output frequencies. These dividers are set by SELA(0,1), SELB(0,1), SELC(0,1) select inputs (see the following Table). For situations were the VCO needs to run at relatively low frequencies and hence might not be stable, assert VCO_SEL low to divide the VCO frequency by 2. This maintains the desired output relationships but provides an enhanced PLL lock range. The CY29972 is also capable of providing inverted output clocks. When INV_CLK is asserted HIGH, QC2 and QC3 output clocks are inverted. These clocks could be used as feedback outputs to the CY29972 or a second PLL device to generate early or late clocks for a specific design. This inversion does not affect the output to output skew. Glitch-Free Output Frequency Transitions Customarily, when output buffers have their internal counters changed “on the fly,” their output clock periods will: 1. contain short or “runt” clock periods. These are clock cycles in which the cycle(s) are shorter in period than either the old or new frequencies to which the cycles are being transitioned. 2. contain stretched clock periods. These are clock cycles in which the cycle(s) are longer in period than either the old or new frequencies to which the cycles are being transitioned. This device specifically includes logic to guarantee that runt and stretched clock pulses do not occur if the device logic levels of any or all of the following pins changed “on the fly” while it is operating: SELA, SELB, SELC, and VCO_SEL. VCO_SEL SELA1 SELA0 QA SELB1 SELB0 QB SELC1 SELC0 QC 0 0 0 VCO/8 0 0 VCO/8 0 0 VCO/4 0 0 1 VCO/12 0 1 VCO/12 0 1 VCO/8 0 1 0 VCO/16 1 0 VCO/16 1 0 VCO/12 0 1 1 VCO/24 1 1 VCO/20 1 1 VCO/16 1 0 0 VCO/4 0 0 VCO/4 0 0 VCO/2 1 0 1 VCO/6 0 1 VCO/6 0 1 VCO/4 1 1 0 VCO/8 1 0 VCO/8 1 0 VCO/6 1 1 1 VCO/12 1 1 VCO/10 1 1 VCO/8 [+] Feedback |
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