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CY62136ESL Datasheet(PDF) 9 Page - Cypress Semiconductor

Part # CY62136ESL
Description  2-Mbit (128 K x 16) Static RAM Ultra low standby power
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY62136ESL Datasheet(HTML) 9 Page - Cypress Semiconductor

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CY62136ESL MoBL®
Document #: 001-48147 Rev. *D
Page 9 of 15
Figure 6. Write Cycle No 1: WE Controlled [22, 23, 24]
Figure 7. Write Cycle 2: CE Controlled [22, 23, 24]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
tHZOE
DATAIN
NOTE 25
tBW
tSCE
DATA I/O
ADDRESS
CE
WE
OE
BHE/BLE
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
DATAIN
tBW
tSA
CE
ADDRESS
WE
DATA I/O
OE
BHE/BLE
NOTE 25
Notes
22. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals are ACTIVE to initiate a write and any of these
signals terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write.
23. Data I/O is high impedance if OE = VIH.
24. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
25. During this period, the I/Os are in output state. Do not apply input signals.
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