Document #: 38-05443 Rev. *E

Page 7 of 16

Switching Characteristics

Over the Operating Range

Parameter [15, 16]

Description

45 ns

Unit

Min

Max

Read Cycle

Read cycle time

45

–

ns

Address to data valid

–

45

ns

Data hold from address change

10

–

ns

CE LOW to data valid

–

45

ns

OE LOW to data valid

–

22

ns

OE LOW to Low Z [17]

5–

ns

OE HIGH to High Z [17, 18]

–18

ns

CE LOW to Low Z [17]

10

–

ns

CE HIGH to High Z [17, 18]

–18

ns

CE LOW to power-up

0

–

ns

CE HIGH to power-down

–

45

ns

BLE/BHE LOW to data valid

–

45

ns

BLE/BHE LOW to Low Z [17]

5–

ns

BLE/BHE HIGH to High Z [17, 18]

–18

ns

Write Cycle [19]

Write cycle time

45

–

ns

CE LOW to write end

35

–

ns

Address setup to write end

35

–

ns

Address hold from write end

0

–

ns

Address setup to write start

0

–

ns

WE pulse width

35

–

ns

BLE/BHE LOW to write end

35

–

ns

Data setup to write end

25

–

ns

Data hold from write end

0

–

ns

WE LOW to High Z [17, 18]

–18

ns

WE HIGH to Low Z [17]

10

–

ns

Notes

16. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Refer application note, AN13842 for more information.

device.

signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.

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