Document #: 38-05445 Rev. *I

Page 3 of 21

Pin Configuration

Figure 1. 48-ball VFBGA (Top View) [1]

Figure 2. 44-pin TSOP II (Top View) [2]

Figure 3. 48-pin TSOP I (512 K × 16/1 M × 8) (Top View) [1, 3]

WE

NC

OE

BHE

BLE

NC

NC

3

2

6

5

4

1

D

E

B

A

C

F

G

H

1

2

3

4

5

6

7

8

9

11

14

31

32

36

35

34

33

37

40

39

38

12

13

41

44

43

42

16

15

29

30

18

17

20

19

27

28

25

26

22

21

23

24

10

OE

BHE

BLE

CE

WE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A15

A14

A13

A12

A11

A10

A9

A8

NC

NC

WE

CE2

NC

BHE

BLE

A18

A17

A7

A6

A5

A4

A3

A2

A1

A16

BYTE

Vss

I/O15/A19

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

Vcc

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

OE

Vss

CE1

A0

Product Portfolio

Product

Range

Speed

(ns)

Power Dissipation

(

A)

f = 1 MHz

Min

Typ [4]

Max

Typ [4]

Max

Typ [4]

Max

Typ [4]

Max

CY62157EV30LL

Industrial/Auto-A

2.2

3.0

3.6

45

1.8

3

18

25

2

8

Auto-E

2.2

3.0

3.6

55

1.8

4

18

35

2

30

Notes

1. NC pins are not connected on the die.

2. The 44-pin TSOP II package has only one chip enable (CE) pin.

3. The BYTE pin in the 48-pin TSOP I package must be tied HIGH to use the device as a 512 K × 16 SRAM. The 48-pin TSOP I package can also be used as a 1 M × 8

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