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CYD18S72V18-167BGC Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CYD18S72V18-167BGC Datasheet(HTML) 9 Page - Cypress Semiconductor |
9 / 52 page FullFlex Document Number: 38-06082 Rev. *K Page 9 of 52 Selection Guide Parameter -200 -167 Unit fMAX[21] 200 167 MHz Maximum access time (clock to data) 3.3 4.0 ns Typical operating current ICC 800[20] 700[20] mA Typical standby current for ISB3 (both ports CMOS level) 210[20] 210[20] mA Pin Definitions Left Port Right Port Description A[20:0]L A[20:0]R Address inputs.[22] DQ[71:0]L DQ[71:0]R Data bus input and output.[23] BE[7:0]L BE[7:0]R Byte select inputs.[24] Asserting these signals enables read and write operations to the corresponding bytes of the memory array. BUSYL BUSYR Port busy output. When there is an address match and both chip enables are active for both ports, an external BUSY signal is asserted on the fifth clock cycles from when the collision occurs. CL CR Clock signal. Maximum clock input rate is fMAX. CE0L CE0R Active LOW chip enable input. CE1L CE1R Active HIGH chip enable input. CQENL CQENR Echo clock enable input. Assert HIGH to enable echo clocking on respective port. CQ0L CQ0R Echo clock signal output for DQ[35:0] for FullFlex72 devices. Echo clock signal output for DQ[17:0] for FullFlex36 devices. Echo clock signal output for DQ[8:0] for FullFlex18 devices. CQ0L CQ0R Inverted echo clock signal output for DQ[35:0] for FullFlex72 devices. Inverted echo clock signal output for DQ[17:0] for FullFlex36 devices. Inverted echo clock signal output for DQ[8:0] for FullFlex18 devices. CQ1L CQ1R Echo clock signal output for DQ[71:36] for FullFlex72 devices. Echo clock signal output for DQ[35:18] for FullFlex36 devices. Echo clock signal output for DQ[17:9] for FullFlex18 devices. CQ1L CQ1R Inverted echo clock signal output for DQ[71:36] for FullFlex72 devices. Inverted echo clock signal output for DQ[35:18] for FullFlex36 devices. Inverted echo clock signal output for DQ[17:9] for FullFlex18 devices. ZQ[1:0]L ZQ[1:0]R VIM output impedance matching input.[25] To use, connect a calibrating resistor between ZQ and ground. The resistor must be five times larger than the intended line impedance driven by the dual port. Assert HIGH or leave DNU to disable VIM. OEL OER Output enable input. This asynchronous signal must be asserted LOW to enable the DQ data pins during read operations. INTL INTR Mailbox interrupt flag output. The mailbox permits communications between ports. The upper two memory locations are used for message passing. INTL is asserted LOW when the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox. LowSPDL LowSPDR Port low speed select input. Assert this pin LOW to disable the DLL. In flow through mode, this pin needs to be asserted low. Notes 20. For 18 Mbit x72 commercial configuration only, refer to Electrical Characteristics on page 19 for complete information. 21. SDR mode with two pipelined stages. 22. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18 and CYD09S36V18 devices have 18 address bits. The CYD09S72V18 device has 17 address bits. The CYD02S36V18 has 16 address bits. 23. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines. 24. The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte enables. 25. The pin ZQ[1] is applicable only for 36 Mbit devices. This pin is DNU for 18 Mbit and lower density devices. [+] Feedback |
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