+5V, 18-Bit, Low-Power, Multichannel,

Oversampling (Sigma-Delta) ADC

6

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Note 1:

Nominal gain is 0.98. This ensures a full-scale input voltage may be applied to the part under all conditions without caus-

ing saturation of the digital output data.

Note 2:

Positive Full-Scale Error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar

and bipolar input ranges. This error does not include the nominal gain of 0.98.

Note 3:

Full-Scale Drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar

input ranges.

Note 4:

Gain Error does not include zero-scale errors. It is calculated as (full-scale error - unipolar offset error) for unipolar ranges

and as (full-scale error - bipolar zero error) for bipolar ranges. This error does not include the nominal gain of 0.98.

Note 5:

Gain-Error Drift does not include unipolar offset drift or bipolar zero drift. It is effectively the drift of the part if zero-scale

error is removed.

Note 6:

Use of the offset DAC does not imply that any input may be taken below AGND.

Note 7:

Additional noise added by the offset DAC is dependent on the filter cutoff, gain, and DAC setting. No noise is added for a

DAC code of 0000.

Note 8:

Guaranteed by design or characterization; not production tested.

Note 9:

The input voltage must be within the Absolute Input Voltage Range specification.

Note 10: All AIN and REFIN pins have identical input structures. Leakage is production tested only for the AIN3, AIN4, AIN5,

CALGAIN, and CALOFF inputs.

Note 11: The dynamic load presented by the MAX1400 analog inputs for each gain setting is discussed in detail in the Switching

Network section. Values are provided for the maximum allowable external series resistance. Note that this value does not

include any additional capacitance added by the user to the MUXOUT_ or ADCIN_ pins.

Note 12: The input voltage range for the analog inputs is with respect to the voltage on the negative input of its respective differen-

tial or pseudo-differential pair. Table 5 shows which inputs form differential pairs.

Note 14: These specifications apply to CLKOUT only when driving a single CMOS load.

Note 15: The burn-out currents require a 500mV overhead between the analog input voltage and both V+ and AGND to operate

correctly.

ELECTRICAL CHARACTERISTICS (continued)

2.4576MHz

1.024MHz

Buffers off

Buffers off

Buffers on

2.4576MHz

1.024MHz

2.43

3.60

Buffers off

Buffers off

Buffers on

Normal mode,

MF1 = 0,

MF0 = 0

4.23

5.75

2.43

3.75

Buffers on

3.70

Buffers on

2X mode,

MF1 = 0,

MF0 = 1

7.4

10.0

CONDITIONS

3.50

5.25

1.88

2.4576MHz

1.024MHz

Buffers off

Buffers off

Buffers on

2.4576MHz

1.024MHz

6.85

Buffers off

Buffers off

Buffers on

4X mode,

MF1 = 1,

MF0 = 0

25.8

33.0

10.8

14.0

Buffers on

25.2

Buffers on

8X mode,

MF1 = 1,

MF0 = 1

mW

26.7

34.0

PD

Power Dissipation

11.7

15.0

10.2

2.95

(Note 18)

10

100

µW

Standby Power Dissipation

1.45

2.55

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

CLK = 0 for 1.024MHz, CLK = 1 for 2.4576MHz.)