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MAX1416EWE Datasheet(PDF) 8 Page - Maxim Integrated Products |
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MAX1416EWE Datasheet(HTML) 8 Page - Maxim Integrated Products |
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8 / 36 page  16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs 8 _______________________________________________________________________________________ ELECTRICAL CHARACTERISTICS—MAX1416 (continued) (VDD = 5V, GND = 0, VREF+ = 2.5V, VREF- = GND, fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1µF, CREF- to GND = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Unbuffered, fCLKIN = 1MHz, gain = 1 to 128 0.45 Buffered, fCLKIN = 1MHz, gain = 1 to 128 0.78 Gain = 1 to 4 0.6 Unbuffered, fCLKIN = 2.4576MHz Gain = 8 to 128 0.6 Gain = 1 to 4 0.95 Buffered, fCLKIN = 2.4576MHz Gain = 8 to 128 1.1 mA Power-Supply Current (Note 12) IDD Power-down mode (Note 13) 16 µA Power-Supply Rejection Ratio PSRR VDD = 4.75V to 5.25V (Note 14) dB EXTERNAL-CLOCK SPECIFICATIONS CLKIN Frequency fCLKIN (Note 15) 400 2500 kHz Duty Cycle 40 60 % INTERNAL-CLOCK TIMING SPECIFICATIONS MAX1416AE__, fCLK = 1MHz (CLK = 0) or 2.4576MHz (CLK = 1) TA = -40 °C to +85 °C ±4 MAX1416C__, fCLK = 1MHz (CLK = 0) or 2.4576MHz (CLK = 1) TA = 0 °C to +70 °C ±4 TA = -40 °C to 0°C±7 Internal-Clock Frequency fCLK MAX1416E__, fCLK = 1MHz (CLK = 0) or 2.4576MHz (CLK = 1) TA= 0 °C to +85°C ±4 % Typical Conversion-Time Variation ∆tCONV tCONV = 1/ODR, CLK = 0 (1MHz), INTCLK = 1 ±0.5 % TIMING CHARACTERISTICS—MAX1416 (Note 16) (Figures 8, 9) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DRDY High Time 500 / fCLKIN s Reset Pulse-Width Low 100 ns DRDY Fall to CS Fall Setup Time t1 0ns CS Fall to SCLK Rise Setup Time t2 120 ns SCLK Fall to DOUT Valid Delay t3 080 ns SCLK Pulse-Width High t4 100 ns SCLK Pulse-Width Low t5 100 ns CS Rise to SCLK Rise Hold Time t6 0ns Bus Relinquish Time After SCLK Rising Edge t7 60 ns SCLK Fall to DRDY Rise Delay t8 100 ns |
Similar Part No. - MAX1416EWE |
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Similar Description - MAX1416EWE |
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