10 _____________________________________________________________________________________

1Gbps to 11.3Gbps, SFP+ Laser Driver

with Laser Impedance Mismatch Tolerance

Pin Configuration

Pin Description

23

24

22

21

8

7

9

10

1

2

TIN-

4

5

6

17

18

16

14

13

TOUT+

TOUT-

TOUT-

MAX3946

3

15

TIN+

20

11 TOUT+

19

THIN QFN

(4mm × 4mm)

TOP VIEW

+

*EP

*EXPOSED PAD CONNECTED TO GROUND.

PIN

NAME

FUNCTION

1, 15

Power Supply. Provides supply voltage to the digital block.

2

DISABLE

Disable Input, CMOS. Set to logic-low for normal operation. Logic-high or open disables both the

3

FAULT

Fault Output, Open Drain. Logic-high indicates a fault condition. FAULT remains high even after the

fault condition has been removed. A logic-low occurs when the fault condition has been removed and

a 4.7kI to 10kI resistor.

4

BMAX

Analog Laser Bias-Current Limit. A resistive voltage-divider connected among BMON, BMAX, and

ground sets the maximum allowed laser bias current limit. The voltage at BMAX is internally com-

pared to 1.2V bandgap reference voltage.

5

BMON

Bias Current-Monitor Output. Current out of this pin develops a ground-referenced voltage across

external resistor(s) that is proportional to the laser bias current. The current sourced by this pin is

typically 1/100th the BIAS pin current.

6, 7, 12, 13

Power Supply. Provides supply voltage to the output block.

8, 9

TOUT-

10, 11

TOUT+

14

BIAS

16

CSEL

Chip-Select Input, CMOS. Setting CSEL to logic-high starts a cycle. Setting CSEL to logic-low ends

17

SDA

Serial-Data Bidirectional Input, CMOS. Open-drain output. This pin has a 75kI internal pullup, but it

requires an external 4.7kI to 10kI pullup resistor. (Data line-collision protection is implemented.)