Power-Supply Sequencing and

Overvoltage Protection

Caution: Do not exceed the absolute maximum rat-

ings because stresses beyond the listed ratings

may cause permanent damage to the devices.

Proper power-supply sequencing is recommended for

all CMOS devices. Always apply V+ before applying

analog signals, especially if the analog signal is not cur-

rent limited. If this sequencing is not possible, and if the

analog inputs are not current limited to <20mA, add a

small-signal diode (D1) as shown in Figure 1. If the ana-

log signal can dip below GND, add D2. Adding protec-

tion diodes reduces the analog range to a diode drop

(about 0.7V) below V+ (for D1), and a diode drop above

ground (for D2). On-resistance increases slightly at low

supply voltages. Maximum supply voltage (V+) must not

exceed +6V.

Adding protection diode D2 causes the logic threshold

to be shifted relative to GND. TTL compatibility is not

guaranteed when D2 is added.

Protection diodes D1 and D2 also protect against some

overvoltage situations. With Figure 1’s circuit, if the sup-

ply voltage is below the absolute maximum rating, and

if a fault voltage up to the absolute maximum rating is

applied to an analog signal pin, no damage will result.

been powered with a minimum of 1.5V to ensure proper

operation of the device.

Low-Voltage, Dual DPDT/Quad SPDT

Analog Switches in QFN

8

_______________________________________________________________________________________

tr < 5ns

tf < 5ns

50%

LOGIC

INPUT

300

Ω

COM_

GND

IN_

(

)

0

NO_

OR NC_

SWITCH

OUTPUT

LOGIC

INPUT

LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES

THAT HAVE THE OPPOSITE LOGIC SENSE.

V+

35pF

V+

MAX4699

MAX4701

MAX4702

Figure 2. Switching Time

50%

LOGIC

INPUT

LOGIC

INPUT

300

Ω

GND

NO_

IN_

NC_

V+

V+

35pF

COM_

MAX4699

MAX4701

MAX4702

Figure 3. Break-Before-Make Interval

Test Circuits/Timing Diagrams