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MAX7370 Datasheet(PDF) 10 Page - Maxim Integrated Products |
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MAX7370 Datasheet(HTML) 10 Page - Maxim Integrated Products |
10 / 37 page ���������������������������������������������������������������� Maxim Integrated Products 10 MAX7370 8 x 8 Key-Switch Controller and LED Driver/GPIOs with I2C Interface and High Level of ESD Protection Keyscan Controller Key inputs are scanned statically, not dynamically, to ensure low-EMI operation. Since inputs only toggle in response to switch changes, the key matrix can be routed closer to sensitive circuit nodes. The keyscan controller debounces and maintains a FIFO buffer of keypress and release events (including auto- repeated keypresses, if autorepeat is enabled). Table 2 shows the key-switch order. The user-programmable key- switch debounce time and autosleep timer are derived from the 64kHz clock, which in turn is derived from the 128kHz oscillator. Time delay for autorepeat and key- switch interrupt is based on the key-switch debounce time. There is no limitation for the number of keys pressed simultaneously as long as no ghost keys are generated. If the application requires fewer keys to be scanned, the unused key-switch ports can be configured as GPIOs. Keys FIFO Register (0x00) The Keys FIFO register contains the information pertain- ing to the status of the keys FIFO, as well as the key events that have been debounced. See Table 7. Bits D[5:0] denote which of the 64 keys have been debounced and the keys are numbered as shown in Table 2. Bit D7 indicates if there is more data in the FIFO, except when D[5:0] indicate key 63 or key 62. When D[5:0] indi- cate key 63 or key 62, the host should read the FIFO one more time to determine whether there is more data in the FIFO. Use key 62 and key 63 for rarely used keys. D6 indicates if it is a keypress or release event, except when D[5:0] indicate key 63 or key 62. Reading the keyscan FIFO clears the interrupt (INT), depending on the setting of bit D5 in the configuration register (0x01). Configuration Register (0x01) The Configuration register controls the I2C bus time- out feature, enables key-release detection, enables autowake, and determines how INT is deasserted. Write to bit D7 to put the device into sleep mode or operating mode. Autosleep and autowake, when enabled, also change the status of D7. See Table 8. Debounce Register (0x02) The Debounce register sets the keypress and key- release time for each debounce cycle. Bits D[3:0] set the debounce time for keypresses, while bits D[7:4] set the debounce time for key releases. Both debounce times are configured in increments of 2ms starting at 2ms and ending at 32ms. See Table 9. Interrupt Register (0x03) The Interrupt register contains information related to the settings of the interrupt request function, as well as the sta- tus of the INT output. If bits D[7:0] are set to 0x00, the INT is disabled. There are two types of interrupts, the FIFO- based interrupt and time-based interrupt. Set bits D[4:0] to assert interrupts at the end of the selected number of debounce cycles following a key event. See Table 10. This number ranges from 1–31 debounce cycles. Setting bits D[5:7] set the FIFO-based interrupt when there are 2–14 key events stored in the FIFO. Both interrupts can be configured simultaneously and INT asserts depending on which condition is met first. INT deasserts depending on the status of bit D5 in the configuration register. Autorepeat Register (0x05) The device autorepeat feature notifies the host that at least one key has been pressed for a continuous period. The Autorepeat register enables or disables this feature, sets the time delay after the last key event before the key- repeat code (0x7E) is entered into the FIFO, and sets Table 2. Key-Switch Mapping PIN COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7 ROW0 KEY 0 KEY 8 KEY 16 KEY 24 KEY 32 KEY 40 KEY 48 KEY 56 ROW1 KEY 1 KEY 9 KEY 17 KEY 25 KEY 33 KEY 41 KEY 49 KEY 57 ROW2 KEY 2 KEY 10 KEY 18 KEY 26 KEY 34 KEY 42 KEY 50 KEY 58 ROW3 KEY 3 KEY 11 KEY 19 KEY 27 KEY 35 KEY 43 KEY 51 KEY 59 ROW4 KEY 4 KEY 12 KEY 20 KEY 28 KEY 36 KEY 44 KEY 52 KEY 60 ROW5 KEY 5 KEY 13 KEY 21 KEY 29 KEY 37 KEY 45 KEY 53 KEY 61 ROW6 KEY 6 KEY 14 KEY 22 KEY 30 KEY 38 KEY 46 KEY 54 KEY 62 ROW7 KEY 7 KEY 15 KEY 23 KEY 31 KEY 39 KEY 47 KEY 55 KEY 63 |
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