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ACS8515LC Datasheet(PDF) 11 Page - Semtech Corporation |
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ACS8515LC Datasheet(HTML) 11 Page - Semtech Corporation |
11 / 47 page Revision 2.05/Jan 2001 ã2001 Semtech Corp www.semtech.com 11 ACS8515 LC/P ADVANCED COMMUNCIATIONS FINAL Figure 2: Minimum Input Jitter Tolerance for inputs supporting G.703 compliant sources Table 4: Amplitude and Frequency values for Jitter Tolerance for inputs supporting G.703 compliant sources e p y T. c e p S e d u ti l p m A ) k p - k p I U ( y c n e u q e r F ) z H ( 1 A2 A1 F2 F3 F4 F 1 S DE R O C - 4 4 2 1 - R G 51 . 00 10 0 5k 8k 0 4 1 E3 2 8 . G U T I 5 . 12 . 00 2k 4 . 2k 8 1k 0 0 1 I I I I $ $ 3HDNWRSHDN MLWWHU DQG ZDQGHUDPSOLWXGH ORJ VFDOH -LWWHU DQG ZDQGHU IUHTXHQF\ ORJ VFDOH I I I I $ $ 3HDNWRSHDN MLWWHU DQG ZDQGHUDPSOLWXGH ORJ VFDOH -LWWHU DQG ZDQGHU IUHTXHQF\ ORJ VFDOH Low-speed Output Clock The O2 SEC clock is supplied on a TTL port with a fixed frequency of 19.44 MHz. High-speed Output Clock The O1 SEC clock is supplied on a PECL/LVDS port with spot frequencies of 19.44 MHz, 38.88 MHz, 155.52 MHz, 311.04 MHz and Dig 1 (where Dig 1 is 1.544/2.048 MHz and multiples of 2, 4 and 8 depending on SONET/SDH mode setting). The actual frequency is selectable via the cnfg_differential_outputs register. The O1 port can also support 311.04 MHz, which is enabled via the cnfg_T0_output_enable register. The O1 port can be made LVDS or PECL compatible via the cnfg_differential_outputs register. Frame Sync and Multi-Frame Sync Clocks Frame Sync (8 kHz) and Multi-Frame Sync (2 kHz) clocks will be provided on outputs FrSync and MFrSync. The FrSync and MFrSync clocks have a 50:50 mark space ratio. Output Wander and Jitter Wander and jitter present on the output clocks are dependent on: The magnitude of wander and jitter on the selected input reference clock (in locked mode); The internal wander and jitter transfer characteristic (in locked mode); The jitter on the local oscillator clock; The wander on the local oscillator clock (in Hold-Over mode). |
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