PCF8593T datasheet(4/35 Pages) NXP

Part #	PCF8593T

Description	Low power clock and calendar

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Manufacturer	NXP [NXP Semiconductors]

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PCF8593

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Product data sheet

Rev. 04 — 6 October 2010

4 of 35

NXP Semiconductors

PCF8593

Low power clock and calendar

7.

Functional description

The PCF8593 contains sixteen 8 bit registers with an 8 bit auto-incrementing address

register, an on-chip 32.768 kHz oscillator circuit, a frequency divider and a serial two-line

bidirectional I2C-bus interface.

The first 8 registers (memory addresses 00h to 07h) are designed as addressable 8 bit

parallel registers. The first register (memory address 00h) is used as a control and status

register. The memory addresses 01h to 07h are used as counters for the clock function.

The memory addresses 08h to 0Fh may be programmed as alarm registers or used as

free RAM locations.

7.1 Counter function modes

When the control and status register is programmed, a 32.768 kHz clock mode, a 50 Hz

clock mode or an event-counter mode can be selected.

In the clock modes the hundredths of a second, seconds, minutes, hours, date, month

(four year calendar) and weekday are stored in a Binary Coded Decimal (BCD) format.

The timer register stores up to 99 days. The event counter mode is used to count pulses

applied to the oscillator input (OSCO left open-circuit). The event counter stores up to 6

digits of data.

When one of the counters is read (memory locations 01h to 07h), the contents of all

counters are strobed into capture latches at the beginning of a read cycle. Therefore,

faulty reading of the counter during a carry condition is prevented. When a counter is

written, other counters are not affected.

7.2 Alarm function modes

By setting the alarm enable bit of the control and status register the alarm control register

(address 08h) is activated.

By setting the alarm control register, a dated alarm, a daily alarm, a weekday alarm, or a

timer alarm may be programmed. In the clock modes, the timer register (address 07h)

may be programmed to count hundredths of a second, seconds, minutes, hours, or days.

Days are counted when an alarm is not programmed.

Whenever an alarm event occurs the alarm flag of the control and status register is set. A

timer alarm event will set the alarm flag and an overflow condition of the timer will set the

timer flag. The open-drain interrupt output is switched on (active LOW) when the alarm or

timer flag is set (enabled). The flags remain set until directly reset by a write operation.

When the alarm is disabled (bit 2 of control and status register set logic 0) the alarm

registers at addresses 08h to 0Fh may be used as free RAM.

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