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PCA9561D Datasheet(PDF) 2 Page - NXP Semiconductors |
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PCA9561D Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 17 page Philips Semiconductors Product data sheet PCA9561 Quad 6-bit multiplexed I2C EEPROM DIP switch 2 2004 May 17 FEATURES • Selection of non-volatile register_n as source to MUX_OUT pins via I2C-bus • I2C-bus can override MUX_SELECT pin in selecting output source • 6-bit 5-to-1 multiplexer DIP switch • 4 internal non-volatile registers • Internal non-volatile registers programmable and readable via I2C-bus • 6 open drain multiplexed outputs • 400 kHz maximum clock frequency • Operating supply voltage 3.0 V to 3.6 V • 5 V and 2.5 V tolerant inputs/outputs • Useful for Speed Step® configuration of laptop • 2 address pins, allowing up to 4 devices on the I2C-bus • MUX_IN values readable via I2C-bus • ESD protection exceeds 200 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 • Latch-up testing is done to JESDEC Standard JESD78 which exceeds 100 mA. DESCRIPTION The PCA9561 is a 20-pin CMOS device consisting of four 6-bit non-volatile EEPROM registers, 6 hardware pin inputs and a 6-bit multiplexed output. It is used for DIP switch-free or jumper-less system configuration and supports Mobile and Desktop VID Configuration, where 5 preset values (4 sets of internal non-volatile registers and 1 set of external hardware pins) set processor voltage for operation in various performance or battery conservation sleep modes. The PCA9561 is also useful in server and telecom/networking applications when used to replace DIP switches or jumpers, since the settings can be easily changed via I2C/SMBus without having to power down the equipment to open the cabinet. The non-volatile memory retains the most current setting selected before the power is turned off. The PCA9561 typically resides between the CPU and Voltage Regulator Module (VRM) when used for CPU VID (Voltage IDentification code) configuration. It is used to bypass the CPU-defined VID values and provide a different set of VID values to the VRM, if an increase in the CPU voltage is desired. An increase in CPU voltage combined with an increase in CPU frequency leads to a performance boost of up to 7.5%. Lower CPU voltage reduces power consumption. The main advantage of the PCA9561 over older devices, such as the PCA9559 or PCA9560, is that it contains four internal non-volatile EEPROM registers instead of just one or two, allowing five independent settings which allows a more accurate CPU voltage tuning depending on specific applications. The PCA9561 has 2 address pins, allowing up to 4 devices to be placed on the same I2C-bus or SMBus. PIN CONFIGURATION SW00823 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 SCL SDA A0 MUX_IN_A MUX_IN_B MUX_IN_C MUX_IN_D MUX_IN_E MUX_IN_F GND VDD WP A1 MUX_OUT_A MUX_OUT_B MUX_OUT_C MUX_OUT_D MUX_OUT_F MUX_OUT_E MUX_SELECT 10 PIN DESCRIPTION PIN SYMBOL FUNCTION 1 I2C SCL Serial I2C-bus clock 2 I2C SDA Serial bi-directional I2C-bus data 3 A0 A0 address 4–9 MUX_IN_A–F External inputs to multiplexer 10 GND Ground 11 MUX_SELECT Selects MUX_IN inputs or register contents for MUX_OUT outputs 12–17 MUX_OUT_F–A Open drain multiplexed outputs 18 A1 A1 address 19 WP Non-volatile register write-protect 20 VDD Power supply: +3.0 to +3.6 V ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER 20-Pin Plastic SO –40 to +85 °C PCA9561D PCA9561D SOT163-1 20-Pin Plastic TSSOP –40 to +85 °C PCA9561PW PCA9561 SOT360-1 Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging. ® Speed Step is a registered trademark of Intel Corp. |
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