VSP5612 datasheet(9/47 Pages) TI1

Part #	VSP5612

Description	16-Bit, 4-Channel, CCD/CMOS Sensor Analog Front-End with Timing Generator

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Manufacturer	TI1 [Texas Instruments]

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VSP5610

VSP5611

VSP5612

www.ti.com

SBES021

– JUNE 2011

ELECTRICAL CHARACTERISTICS: VSP5612

All specifications at TA = +25°C, supply voltage = +3.3 V, conversion rate = 17.5 MHz, and four-channel mode, unless

otherwise noted.

VSP5612

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUT

Allowable input voltage

0

VDD

V

Full-scale range

Gain = 1 V/V

1

VPP

Input capacitor

5

pF

DIGITAL INPUT

Positive-going threshold

VT+

DVDD_IO

× 0.7

V

Negative-going threshold

VT–

DVDD_IO

× 0.3

V

Hysteresis (VT+ – VT–)

ΔVT

DVDD_IO

× 0.13

V

Input current

IIN

±1

µA

Input capacitor

5

pF

DIGITAL OUTPUT

IOH = –2 mA

DVDD_IO

– 0.45

V

High-level output voltage

VOH

IOH = –4 mA

DVDD_IO

– 0.50

V

IOH = –8 mA

DVDD_IO

– 0.50

V

IOL = 2 mA

0.35

V

Low-level output voltage

VOL

IOL = 4 mA

0.50

V

IOL = 8 mA

0.65

V

XP1, XP2, XP3, XP4

–1

1

ns

TG output timing skew

Other signals

–2

2

ns

CMOS data output bit rate

80

MHz

LVDS DRIVER (TA, TB, TC, TCLK)

Differential steady-state output

|VOD|

RL = 100 Ω

300

350

400

mV

voltage adjustment range

Differential steady-state output

|VOD|

3

Steps

adjustment step

Differential steady-state output

|VOD|

–30

30

%

voltage tolerance

Change in the steady-state

differential output voltage magnitude

Δ|VOD|

35

mV

between opposite binary states

Steady-state common-mode output

VOC(SS)

RL = 100 Ω

1.125

1.375

V

voltage

Peak-to-peak common-mode output

VOC(PP)

80

150

mV

voltage

Short-circuit output current

IOS

VO = 0 V (VO = TA, TB, TC, TCLK)

–6

±24

mA

VO = 0 V to LVDD

Hi-Z output current

IOZ

±10

µA

(VO = TA, TB, TC, TCLK)

Transition time, differential output

tLR/tLF

0.75

1.5

ns

voltage

TCLK clock rate

8

70

MHz

LVDS RECEIVER (RCLK)

Positive-going differential input

VIT+

100

mV

threshold voltage

Negative-going differential input

VIT–

–100

mV

threshold voltage

RCLK clock rate

1

23.33

MHz

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