MSP430F249-EP datasheet(6/81 Pages) TI

Part #	MSP430F249-EP

Description	MIXED SIGNAL MICROCONTROLLER

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Manufacturer	TI [Texas Instruments]

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MSP430F249-EP

MIXED SIGNAL MICROCONTROLLER

2008

6

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

P4.2/TB2

38

I/O

General-purpose digital I/O / Timer_B, capture: CCI2A/B input, compare: Out2 output

P4.3/TB3

39

I/O

General-purpose digital I/O / Timer_B, capture: CCI3A/B input, compare: Out3 output

P4.4/TB4

40

I/O

General-purpose digital I/O / Timer_B, capture: CCI4A/B input, compare: Out4 output

P4.5/TB5

41

I/O

General-purpose digital I/O / Timer_B, capture: CCI5A/B input, compare: Out5 output

P4.6/TB6

42

I/O

General-purpose digital I/O / Timer_B, capture: CCI6A input, compare: Out6 output

P4.7/TBCLK

43

I/O

General-purpose digital I/O / Timer_B, clock signal TBCLK input

P5.0/UCB1STE/

UCA1CLK

44

I/O

General-purpose digital I/O / USCI B1 slave transmit enable / USCI A1 clock input/output

P5.1/UCB1SIMO/

UCB1SDA

45

I/O

General-purpose digital I/O / USCI B1slave in/master out in SPI mode, SDA I2C data in I2C mode

P5.2/UCB1SOMI/

UCB1SCL

46

I/O

General-purpose digital I/O / USCI B1slave out/master in in SPI mode, SCL I2C clock in I2C mode

P5.3/UCB1CLK/

UCA1STE

47

I/O

General-purpose digital I/O / USCI B1 clock input/output, USCI A1 slave transmit enable

P5.4/MCLK

48

I/O

General-purpose digital I/O / main system clock MCLK output

P5.5/SMCLK

49

I/O

General-purpose digital I/O / submain system clock SMCLK output

P5.6/ACLK

50

I/O

General-purpose digital I/O / auxiliary clock ACLK output

P5.7/TBOUTH/

SVSOUT

51

I/O

General-purpose digital I/O / switch all PWM digital output ports to high impedance − Timer_B TB0 to

TB6/SVS comparator output

P6.0/A0

59

I/O

General-purpose digital I/O / analog input A0 – 12-bit ADC

P6.1/A1

60

I/O

General-purpose digital I/O / analog input A1 – 12-bit ADC

P6.2/A2

61

I/O

General-purpose digital I/O / analog input A2 – 12-bit ADC

P6.3/A3

2

I/O

General-purpose digital I/O / analog input A3 – 12-bit ADC

P6.4/A4

3

I/O

General-purpose digital I/O / analog input A4 – 12-bit ADC

P6.5/A5

4

I/O

General-purpose digital I/O / analog input A5 – 12-bit ADC

P6.6/A6

5

I/O

General-purpose digital I/O / analog input A6 – 12-bit ADC

P6.7/A7/SVSIN

6

I/O

General-purpose digital I/O / analog input A7 – 12-bit ADC/SVS input

XT2OUT

52

O

Output of crystal oscillator XT2

XT2IN

53

I

Input for crystal oscillator XT2

RST/NMI

58

I

Reset input, nonmaskable interrupt input port, or bootstrap loader start (in flash devices).

TCK

57

I

Test clock (JTAG). TCK is the clock input port for device programming test and bootstrap loader start

TDI/TCLK

55

I

Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.

TDO/TDI

54

I/O

Test data output. TDO/TDI data output or programming data input terminal

TMS

56

I

Test mode select. TMS is used as an input port for device programming and test.

VeREF+

10

I

Input for an external reference voltage

VREF+

7

O

Output of positive of the reference voltage in the ADC12

VREF−/VeREF−

11

I

Negativefor the reference voltage for both sources, the internal reference voltage, or an external applied

reference voltage

XIN

8

I

Input for crystal oscillator XT1. Standard or watch crystals can be connected.

XOUT

9

O

Output for crystal oscillator XT1. Standard or watch crystals can be connected.

QFN Pad

NA

QFN package pad connection to DVSS recommended (RTD package only)

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