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MSP430FR5730IPW Datasheet(PDF) 4 Page - Texas Instruments |
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MSP430FR5730IPW Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 64 page  Clock System 16KB 8KB FRAM (’5739, ’5729) (’5735, ‘5725) 4KB (’5731, ‘5721) 1KB RAM (’5739, ’5735) (’5729, ’5725) (’5731, ’5721) 0.5KB MCLK ACLK SMCLK CPUXV2 and Working Registers EEM (S:3+1) PJ.4/XIN PJ.5/XOUT JTAG/ Interface SBW DMA 3Channel Power Management SVS SYS Watchdog MPY32 TA0 TA1 (2)Timer_A 3CC Registers TB0 TB1 TB2 (3)Timer_B 3CC Registers ADC10_B 200KSPS 16channels (12ext/2int) 10Bit DVCC DVSS AVCC AVSS RST/NMI/SBWTDIO RTC_B Comp_D 16channels VCORE MAB MDB TEST/SBWTCK PJ.0/TDO PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK I/OPorts P1/P2 2×8I/Os Interrupt &Wakeup PA 1×16I/Os PA P1.x P2.x I/OPorts P3/P4 1×8I/Os 1x2I/Os Interrupt &Wakeup PB 1×10I/Os PB P3.x P4.x REF CRC eUSCI_A0: UART, IrDA,SPI eUSCI_B0: SPI,I2C Boot ROM Memory Protection Unit eUSCI_A1: UART, IrDA,SPI Clock System 16KB 8KB FRAM (’5737, ’5727) (’5733, ‘5723) 1KB RAM (’5737, ’5733) (’5727, ’5723) MCLK ACLK SMCLK CPUXV2 and Working Registers EEM (S:3+1) PJ.4/XIN PJ.5/XOUT JTAG/ Interface SBW DMA 3Channel Power Management SVS SYS Watchdog MPY32 TA0 TA1 (2)Timer_A 3CC Registers TB0 TB1 TB2 (3)Timer_B 3CC Registers DVCC DVSS AVCC AVSS RST/NMI/SBWTDIO RTC_B Comp_D 16channels VCORE MAB MDB TEST/SBWTCK PJ.0/TDO PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK I/OPorts P1/P2 2×8I/Os Interrupt &Wakeup PA 1×16I/Os PA P1.x P2.x I/OPorts P3/P4 1×8I/Os 1x2I/Os Interrupt &Wakeup PB 1×10I/Os PB P3.x P4.x CRC eUSCI_A0: UART, IrDA,SPI eUSCI_B0: SPI,I2C Boot ROM Memory Protection Unit eUSCI_A1: UART, IrDA,SPI MSP430FR573x MSP430FR572x SLAS639 – APRIL 2011 www.ti.com Functional Block Diagram – MSP430FR5721IRHA, MSP430FR5725IRHA, MSP430FR5729IRHA MSP430FR5731IRHA MSP430FR5735IRHA, MSP430FR5739IRHA Functional Block Diagram – MSP430FR5723IRHA, MSP430FR5727IRHA MSP430FR5733IRHA, MSP430FR5737IRHA 4 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated |
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