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PMS430E112JL Datasheet(PDF) 7 Page - Texas Instruments |
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PMS430E112JL Datasheet(HTML) 7 Page - Texas Instruments |
7 / 33 page MSP430x11x MIXED SIGNAL MICROCONTROLLERS SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 76 5 4 0 OFIE WDTIE 32 1 rw-0 rw-0 rw-0 Address 0h NMIIE WDTIE: Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. OFIE: Oscillator fault enable NMIIE: (Non)maskable interrupt enable interrupt flag register 1 76 5 4 0 OFIFG WDTIFG 32 1 rw-0 rw-1 rw-(0) Address 02h NMIIFG WDTIFG: Set on Watchdog Timer overflow (in watchdog mode) or security key violation. Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode. OFIFG: Flag set on oscillator fault NMIIFG: Set via RST/NMI-pin Legend rw: rw-0,1: Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC SFR bit is not present in device. rw-(0,1): Bit can be read and written. It is Reset or Set by POR |
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